• The KIPS Transactions:PartA
• /
• v.17A no.3
• /
• pp.153-158
• /
• 2010

Most of software developers use the GNU Debugger (GDB) in order to debug code execution. The GDB supports a remote debugging environment through serial communication. However, in embedded systems, the speed is limited in the serial communication. Due to this reason, the serial communication is rarely used for the debugging purpose. To solve this problem, many embedded systems adapt the JTAG and the USB interface. This paper proposes debugging environment via USB-JTAG interface to debug the EISC processor, and introduces how the USB interface works on the GDB and how the JTAG module handles debugging packets.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.3A
• /
• pp.226-232
• /
• 2005

An on-chip debugging unit is proposed aiming performance enhancement of JTAG-based SoC systems. The proposed unit comprises a JTAG module and a core breaker. The IEEE 1149.1 standard has been modified and applied to the new JTAG module. The proposed unit eliminates redundant clock cycles included in the TAP command execution stage. TAP execution commands are repeatedly issued to perform debugging of complicated SoC systems. Simulation on the proposed unit shows some 14% performance enhancement and 50% gate count reduction compared to the conventional ones.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.7
• /
• pp.65-75
• /
• 2011

As the technology of SoC design has been developed, the debugging is more and more important and users want a fast and reliable debugger. This paper deals with an implementation of the fast debugger which can reduce a debugging processing cycle by designing a modified JTAG suitable for a new RISC processor debugger. Designed JTAG is embedded to the OCD of Core-A and works with SW debugger. We confirmed the functions and reliability of the debugger. By comparing to the original JTAG system, the debugging processing cycle of the proposed JTAG is reduced at 8.5~72.2% by each debugging function. Further more, the gate count is reduced at 31.8%.

• KIPS Transactions on Computer and Communication Systems
• /
• v.3 no.2
• /
• pp.31-42
• /
• 2014

Debugger systems are necessary to apply dynamic program analysis when evaluating security properties of embedded system software. It may be possible to make the use of software-based debugger and/or DBI framework if target devices support general purpose operating systems, however, constraints on applicability as well as environmental transparency might be incurred thereby hindering overall analyzability. Analysis with JTAG (IEEE 1149.1) debugging devices can overcome these difficulties in that no change would be involved in terms of internal software environment. In that sense, JTAG API can facilitate to practically perform dynamic program analysis for evaluating security properties of target device software. In this paper, we introduce an implementation of JTAG API to enable analysis of ARM core based embedded systems. The API function set includes the categories of debugger and target device controls: debugging environment and operation. To verify API applicability, we also provide example analysis tool implementations: our JTAG API could be used to build kernel function fuzzing and live memory forensics modules.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.11
• /
• pp.115-121
• /
• 2004

GenJTAG implemented in this paper is an automatic web-based boundary scan circuit generator. GenJTAG supports all the public instructions for the boundary scan technique, and also private instructions for other DFT techniques to be applied. Users can easily edit the generated boundary scan circuit code because it is described in behavioral level with the Verilog-HDL. GenJTAG has another advantage that any one can generate the boundary scan circuit by simply accessing to the web site.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.14 no.10
• /
• pp.5123-5129
• /
• 2013

In this paper, it is proposed that JTAG fault injection environment and the results of the classification techniques that the reliability of embedded systems can be tested. As applying these, this is possible to quantitative analysis of vulnerable factor for system. The quantitative analysis for the degree of vulnerability of system is evaluated by faults errors, and failures classification schemes. When applying these schemes, it is possible to verify process and classify for fault that might occur in the system.

• Proceedings of the KIEE Conference
• /
• 2003.07d
• /
• pp.2756-2758
• /
• 2003

ARM CORE용 칩으로 철도 종합 제어 부분에 이용될 수 있는 main processor 부분을 설계하고, JTAG 기술을 이용하여 그 안정성과 틸팅 기술에 이용될 수 있는 process를 사전 단계에서 bebugging 해보고, 이에 따른 신호 및 성능을 JTAG(Boundary Scan)을 이용하여 시스템의 신호와 파형을 시험 평가한다. 또한 예비 단계로의 JTAG 검증 가능성 여부를 알아보고자 한다. 철도 종합 제어 시스템의 신호 및 정확성을 측정해 보기 위한 선행 연구라 할 수 있다.

• Proceedings of the KAIS Fall Conference
• /
• 2007.11a
• /
• pp.256-258
• /
• 2007

내장 소프트웨어는 실제 시스템의 자원과 원격지의 시스템의 환경에 민감하므로 실제 시스템과 동일한 환경에서 디버깅해야 한다. 그러나 대부분의 내장 소프트웨어를 탑재하는 실제 시스템은 시스템 상태를 조사하거나 제어하는 것이 제한되어 있는 소프트웨어를 디버깅하는 것은 매우 어렵다. 본 논문에서는 원격지의 USB와 실제 시스템의 JTAG을 기반으로 내장 소프트웨어를 디버깅할 수 있는 어뎁터 제안한다. 본 논문은 실제 시스템내의 내장 소프트웨어를 디버깅할 수 있는 경제적인 인터페이싱 환경을 제공한다.

• Korea Multimedia Society
• /
• v.7 no.3
• /
• pp.12-23
• /
• 2003

• Proceedings of the IEEK Conference
• /
• summer
• /
• pp.61-65
• /
• 2004

An on-chip debugging unit is proposed aiming performance enhancement of JTAG-based SoC systems. The proposed unit comprises a JTAG module and a core breaker. The IEEE 1149.1 standard has been modified and applied to the new JTAG module. The proposed unit eliminates redundant clock cycles included in the TAP command execution stage reducing overall debugging time. TAP execution commands are repeatedly issued to perform debugging of complicated SoC systems. Simulation on the proposed unit shows some $14\%$ performance enhancement and $50\%$ gate count reduction compared to the conventional ones.