• Title/Summary/Keyword: JGB

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The Effects of Levelers on Electroplating of Thin Copper Foil for FCCL (전기도금법을 이용한 FCCL용 구리박막 제조시 레벨러의 영향 연구)

  • Kang, In-Seok;Koo, Yeon-Soo;Lee, Jae-Ho
    • Journal of the Microelectronics and Packaging Society
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    • v.19 no.2
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    • pp.67-72
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    • 2012
  • In recent days, the wire width of IC is narrowed and the degree of integration of IC is increased to obtain the higher capacity of the devices in electronic industry. And then the surface quality of FCCL(Flexible Copper Clad Laminate) became increasingly important. Surface defects on FCCL are bump, scratch, dent and so on. In particular, bumps cause low reliability of the products. Even though there are bumps on the surface, if leveling characteristic of plating solution is good, it does not develop significant bump. In this study, the leveling characteristics of additives are investigated. The objective of study is to improve the leveling characteristic and reduce the surface step through additives and plating conditions. The additives in the electrodeposition bath are critical to obtain flat surface and free of defects. In order to form flat copper surface, accelerator, suppressor and leveler are added to the stock solution. The reason for the addition of leveler is planarization surface and inhibition of the formation of micro-bump. Levelers (SO(Safranin O), MV(Methylene Violet), AB(Alcian Blue), JGB(Janus Green B), DB(Diazine Black) and PVP(Polyvinyl Pyrrolidone) are used in copper plating solution to enhance the morphology of electroplated copper. In this study, the nucleation and growth behavior of copper with variation of additives are studied. The leveling characteristics are analyzed on artificially fabricated Ni bumps.

Effect of Additives on the Hardness of Copper Electrodeposits in Acidic Sulfate Electrolyte (황산구리 전착에서의 첨가제가 구리전착층의 경도에 미치는 영향)

  • Min, Sung-Ki;Lee, Jeong-Ja;Hwang, Woon-Suk
    • Corrosion Science and Technology
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    • v.10 no.4
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    • pp.143-150
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    • 2011
  • Copper electroplating has been applied to various fields such as decorative plating and through-hole plating. Technical realization of high strength copper preplating for wear-resistant tools and molds in addition to these applications is the aim of this work. Brighters and levelers, such as MPSA, Gelatin, Thiourea, PEG and JGB, were added in copper sulfate electrolyte, and the effects of these organic additives on the hardness were evaluated. All additives in this work were effective in increasing the hardness of copper electrodeposits. Thiourea increased the hardness up to 350 VHN, and was the most effective accelarator in sulfate electrolyte. It was shown from the X-ray diffraction analysis that preferred orientation changed from (200) to (111) with increasing concentration of organic additives. Crystallite size decreased with increasing concentration of additive. Hardness was increased with decreasing crystallite size, and this result is consistent with Hall-Petch relationship, and it was apparent that the hardening of copper electrodeposits results from the grain refining effect.

Characteristic of Through Silicon Via's Seed Layer Deposition and Via Filling (실리콘 관통형 Via(TSV)의 Seed Layer 증착 및 Via Filling 특성)

  • Lee, Hyunju;Choi, Manho;Kwon, Se-Hun;Lee, Jae-Ho;Kim, Yangdo
    • Korean Journal of Materials Research
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    • v.23 no.10
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    • pp.550-554
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    • 2013
  • As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.