• Title/Summary/Keyword: Ion etching

검색결과 731건 처리시간 0.025초

펄스-역펄스 전착법을 이용한 SiP용 via의 구리 충진에 관한 연구 (Electroplating of Copper Using Pulse-Reverse Electroplating Method for SiP Via Filling)

  • 배진수;장근호;이재호
    • 마이크로전자및패키징학회지
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    • 제12권2호
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    • pp.129-134
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    • 2005
  • SiP의 3D패키지에 있어서 구리도금은 매우 중요한 역할을 한다 이러한 구리 도금의 조건을 알아보기 위하여 조건이 다른 전해질에서 전기화학적 I-V특성을 분석하였다. 첨가제로 억제제와 촉진제의 특성을 분석하였다. 3D 패키지에 있어서 직경 50, 75, $100{\mu}m$의 via를 사용하였다. Via의 높이는 $100{\mu}m$로 동일하였다. Via의 내부는 확산방지층으로 Ta을 전도성 씨앗층으로 Cu를 magnetron 스퍼터링 방법으로 도포하였다. 직류, 펄스, 펄스-역펄스 등 전류의 파형을 변화시키면서 구리 도금을 하였다. 직류만 사용하였을 경우에는 결함 없이 via가 채워지지 않았으며 펄스도금을 한 경우 구리 충진이 개선을 되었으나 결함이 발생하였다. 펄스-역펄스를 사용한 경우 결함 없는 구리 충진층을 얻을 수 있었다.

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Gate-Induced Drain Leakage를 줄인 새로운 구조의 고성능 Elevated Source Drain MOSFET에 관한 분석 (Analysis of a Novel Elevated Source Drain MOSFET with Reduced Gate-Induced Drain Leakage and High Driving Capability)

  • 김경환;최창순;김정태;최우영
    • 대한전자공학회논문지SD
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    • 제38권6호
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    • pp.390-397
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    • 2001
  • GIDL(Gate-Induced Drain-Leakage)을 줄일 수 있는 새로운 구조의 ESD(Elevated Source Drain) MOSFET을 제안하고 분석하였다. 제안된 구조는 SDE(Source Drain Extension) 영역이 들려진 형태를 갖고 있어서 SDE 임플란트시 매우 낮은 에너지 이온주입으로 인한 저활성화(low-activation) 효과를 방지 할 수 있다. 제안된 구조는 건식 식각 및 LAT(Large-Angle-Tilted) 이온주입 방법을 사용하여 소오스/드레인 구조를 결정한다. 기존의 LDD MOSFET과의 비교 시뮬레이션 결과, 제안된 ESD MOSFET은 전류 구동능력은 가장 크면서 GIDL 및 DIBL(Drain Induced Barrier Lowering) 값은 효과적으로 감소시킬 수 있음을 확인하였다. GIDL 전류가 감소되는 원인으로는 최대 전계의 위치가 드레인 쪽으로 이동함에 따라 최대 밴드간 터널링이 일어나는 곳에서의 최대 전계값이 감소되기 때문이다.

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$CCI_4$ 를 사용하여 베이스를 탄소도핑한 AlGaAs/GaAs HBT의 제작 및 특성 (Fabrication and Characteristic of C-doped Base AlGaAs/GaAs HBT using Carbontetrachloride $CCI_4$)

  • 손정환;김동욱;홍성철;권영세
    • 전자공학회논문지A
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    • 제30A권12호
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    • pp.51-59
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    • 1993
  • A 4${\times}10^{19}cm^{3}$ carbon-doped base AlGaAs/GaAs HBY was grown using carbontetracholoride(CCl$_4$) by atmospheric pressure MOCVD. Abruptness of emitter-base junction was characterized by SIMS(secondary ion mass spectorscopy) and the doping concentration of base layer was confirmed by DXRD(double crystal X-ray diffractometry). Mesa-type HBTs were fabricated using wet etching and lift-off technique. The base sheet resistance of R$_{sheet}$=550${\Omega}$/square was measured using TLM(transmission line model) method. The fabricated transistor achieved a collector-base junction breakdown voltage of BV$_{CBO}$=25V and a critical collector current density of J$_{O}$=40kA/cm$^2$ at V$_{CE}$=2V. The 50$\times$100$\mu$$^2$ emitter transistor showed a common emitter DC current gain of h$_{FE}$=30 at a collector current density of JS1CT=5kA/cm$^2$ and a base current ideality factor of ηS1EBT=1.4. The high frequency characterization of 5$\times$50$\mu$m$^2$ emitter transistor was carried out by on-wafer S-parameter measurement at 0.1~18.1GHz. Current gain cutoff frequency of f$_{T}$=27GHz and maximum oscillation frequency of f$_{max}$=16GHz were obtained from the measured Sparameter and device parameters of small-signal lumped-element equivalent network were extracted using Libra software. The fabricated HBT was proved to be useful to high speed and power spplications.

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저전압 구동용 전기스위치와 미러 어레이 응용을 위한 새로운 표면미세가공기술 (A New Surface Micromachining Technology for Low Voltage Actuated Switch and Mirror Arrays)

  • 박상준;이상우;김종팔;이상우;이상철;김성운;조동일
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 하계학술대회 논문집 G
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    • pp.2518-2520
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    • 1998
  • Silicon can be reactive ion etched (RIE) either isotropically or anisotropically. In this paper, a new micromachining technology combining these two etching characteristics is proposed. In the proposed method, the fabrication steps are as follows. First. a polysilicon layer, which is used as the bottom electrode, is deposited on the silicon wafer and patterned. Then the silicon substrate is etched anisotropically to a few micrometer depth that forms a cavity. Then an PECVD oxide layer is deposited to passivate the cavity side walls. The oxide layers at the top and bottom faces are removed while the passivation layers of the side walls are left. Then the substrate is etched again but in an isotropic etch condition to form a round trench with a larger radius than the anisotropic cavity. Then a sacrificial PECVD oxide layer is deposited and patterned. Then a polysilicon structural layer is deposited and patterned. This polysilicon layer forms a pivot structure of a rocker-arm. Finally, oxide sacrificial layers are etched away. This new micromachining technology is quite simpler than conventional method to fabricate joint structures, and the devices that are fabricated using this technology do not require a flexing structure for motion.

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Plasma Assisted ALD 장비 계발과 PAALD법으로 증착 된 TaN 박막의 전기적 특성 (Development of Plasma Assisted ALD equipment and Electrical Characteristic of TaN thin film deposited PAALD method)

  • 도관우;김경민;양충모;박성근;나경일;이정희;이종현
    • 반도체디스플레이기술학회지
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    • 제4권2호
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    • pp.39-43
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    • 2005
  • In the study, in order to deposit TaN thin film for diffusion barrier and bottom electrode we made the Plasma Assisted ALD equipment and confirmed the electrical characteristics of TaN thin films grown PAALD method. Plasma Assisted ALD equipment depositing TaN thin film using PEMAT(pentakis(ethylmethlyamino) tantalum) precursor and NH3 reaction gas is shown that TaN thin film deposited high density and amorphous phase with XRD measurement. The degree of diffusion and reaction taking place in Cu/TaN (deposited using 150W PAALD)/$SiO_{2}$/Si systems with increasing annealing temperature was estimated for MOS capacitor property and the $SiO_{2}$, (600${\AA}$)/Si system surface analysis by C-V measurement and secondary ion material spectrometer (SIMS) after Cu/TaN/$SiO_{2}$ (400 ${\AA}$) layer etching. TaN thin film deposited PAALD method diffusion barrier have a good diffusion barrier property up to 500$^{\circ}C$.

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450 mm 웨이퍼 공정용 System의 기하학적 구조에 따른 플라즈마 균일도 모델링 분석 (Plasma Uniformity Numerical Modeling of Geometrical Structure for 450 mm Wafer Process System)

  • 양원균;주정훈
    • 한국진공학회지
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    • 제19권3호
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    • pp.190-198
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    • 2010
  • 450 mm의 웨이퍼 공정용 플라즈마 장비의 개발을 위하여 안테나 형상, 챔버의 직경, 웨이퍼까지의 거리에 따른 플라즈마 균일도를 Ar과 $CF_4$에 대하여 축대칭 2차원으로 수치 모델링하였다. 챔버의 종횡비를 직경, 기판까지의 거리, 배기구의 면적으로 나누어서 결정하고 여기에 안테나 구조를 변경하여서 최적의 플라즈마 균일도를 갖는 조건을 도출하였다. Drift diffusion식과 준중성 조건을 이용한 간략화를 이용하였으며 표면 재결합과 식각 반응을 이온에너지의 함수로 처리하였다. 반응기판 표면에서의 플라즈마 밀도 균일도는 기판 홀더와 챔버 벽면과의 거리, 기판과 소스와의 거리가 멀수록 좋아졌으며, 안테나의 디자인이 4 turn으로 1층인 경우, 두 번째, 네 번째 turn만 사용하여 전류비 1 : 4에서 기판표면에서의 플라즈마 균일도를 4.7%까지 낮출 수 있었다. Ar과 $CF_4$의 반경 방향으로 전자 온도 균일도 50%, 전자 밀도 균일도 19%의 차이가 있었다.

이중 모드 결합에 의한 이동 통신 기기용 SAW 필터 (Double-Mode SAW Filter for Mobile Communication System)

  • 정영지;진익수;황금찬
    • 한국통신학회논문지
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    • 제18권4호
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    • pp.468-480
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    • 1993
  • 본 논문에서는 2개의 동일한 1-Port 형 공진기를 병렬로 근접배치시킨 이중모드 SAW 공진기의 설계를 위하여, 우선, 결합 모드이론에 의한 1-Port 형 공진기의 특성을 기초로 하여, 도파로 모델을 적용한 이중모드 SAW 공진기의 특성을 분석하였으며, 이를 이용해서 중심 주파수가 150.15MHz이고 대역폭이 80KHz인 2-Pole 및 4-Pole 협대역 필터를 설계.제작 하였다. 이중모드 SAW 필터를 설계변수를 달리하여 여러 번 제작.실험하여 실험치와 이론치를 비교함으로써, 제품 설계에 사용 가능한 실험적 설계 특성을 얻었으며, 이동통신기기에서 사용될 수 있는 헙대역 통과 필터를 구현하였다. DMS 공진기를 구성한 압전 기판으로는 높은 주파수에서도 온도변화에 의한 주파수 이동 및 물성의 변화가 적은 ST-cut quartz(수정)를 선택하였으며, 필터의 제작은 정확한 전극구조를 얻기 위하여 고해상도 사진 식각법과 전극의 수직식각특성이 우수한 이온반응 식각법(Reactive Ion Etching)을 적용하였다.

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초소형 광정보저장기기용 웨이퍼 스케일 대물렌즈 제작을 위한 회절광학소자 성형기술 개발 (Fabrication of diffractive optical element for objective lens of small form factor data storage device)

  • 배형대;임지석;정기봉;한정원;유준모;박노철;강신일
    • 한국소성가공학회:학술대회논문집
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    • 한국소성가공학회 2005년도 금형가공,미세가공,플라스틱가공 공동 심포지엄
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    • pp.35-40
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    • 2005
  • The demand for small and high-capacity optical data storage devices has rapidly increased. The areal density of optical disk is increased using higher numerical aperture objective lens and shorter wavelength source. A wafer-scale stacked micro objective lens with a numerical aperture of 0.85 and a focal length of 0.467mm for the 405nm blue- violet laser was designed and fabricated. A diffractive optical element (DOE) was used to compensate the spherical aberration of the objective lens. Among the various fabrication methods for micro DOE, the UV-replication process is more suitable for mass-production. In this study, an 8-stepped DOE pattern as a master was fabricated by photolithography and reactive ion etching process. A flexible mold was fabricated for improving the releasing properties and shape accuracy in UV-molding process. In the replication process, the effects of exposing time and applied pressure on the replication quality were analyzed. Finally, the shapes of master, mold and molded pattern were measured by optical scanning profiler. The deviation between the master and the molded DOE was less than 0.1um. The efficiency of the molded DOE was measured by DOE efficiency measurement system which consists of laser source, sample holder, aperture and optical power meter, and the measured value was $84.5\%$.

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연마제 특성에 따른 차세대 금속배선용 Al CMP (chemical mechanical planarization) 슬러리 평가 (Evaluation of Al CMP Slurry based on Abrasives for Next Generation Metal Line Fabrication)

  • 차남구;강영재;김인권;김규채;박진구
    • 한국재료학회지
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    • 제16권12호
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    • pp.731-738
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    • 2006
  • It is seriously considered using Al CMP (chemical mechanical planarization) process for the next generation 45 nm Al wiring process. Al CMP is known that it has a possibility of reducing process time and steps comparing with conventional RIE (reactive ion etching) method. Also, it is more cost effective than Cu CMP and better electrical conductivity than W via process. In this study, we investigated 4 different kinds of slurries based on abrasives for reducing scratches which contributed to make defects in Al CMP. The abrasives used in this experiment were alumina, fumed silica, alkaline colloidal silica, and acidic colloidal silica. Al CMP process was conducted as functions of abrasive contents, $H_3PO_4$ contents and pressures to find out the optimized parameters and conditions. Al removal rates were slowed over 2 wt% of slurry contents in all types of slurries. The removal rates of alumina and fumed silica slurries were increased by phosphoric acid but acidic colloidal slurry was slightly increased at 2 vol% and soon decreased. The excessive addition of phosphoric acid affected the particle size distributions and increased scratches. Polishing pressure increased not only the removal rate but also the surface scratches. Acidic colloidal silica slurry showed the highest removal rate and the lowest roughness values among the 4 different slurry types.

3차원 LIGA 미세구조물 제작을 위한 마이크로 액추에이터 내장형 X-선 마스크 (Deep X-ray Mask with Integrated Micro-Actuator for 3D Microfabrication via LIGA Process)

  • 이광철;이승섭
    • 대한기계학회논문집A
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    • 제26권10호
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    • pp.2187-2193
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    • 2002
  • We present a novel method for 3D microfabrication with LIGA process that utilizes a deep X-ray mask in which a micro-actuator is integrated. The integrated micro-actuator oscillates the X-ray absorber, which is formed on the shuttle mass of the micro-actuator, during X-ray exposures to modify the absorbed dose profile in X-ray resist, typically PMMA. 3D PMMA microstructures according to the modulated dose contour are revealed after GG development. An X-ray mask with integrated comb drive actuator is fabricated using deep reactive ion etching, absorber electroplating, and bulk micromachining with silicon-on-insulator (SOI) wafer. 1mm $\times$ 1 mm, 20 $\mu$m thick silicon shuttle mass as a mask blank is supported by four 1 mm long suspension beams and is driven by the comb electrodes. A 10 $\mu$m thick, 50 $\mu$m line and spaced gold absorber pattern is electroplated on the shuttle mass before the release step. The fundamental frequency and amplitude are around 3.6 kHz and 20 $\mu$m, respectively, for a do bias of 100 V and an ac bias of 20 $V_{p-p}$ (peak-peak). Fabricated PMMA microstructure shows 15.4 $\mu$m deep, S-shaped cross section in the case of 1.6 kJ $cm^{-3}$ surface dose and GG development at 35$^{\circ}C$ for 40 minutes.