• Title/Summary/Keyword: Inverting circuit

Search Result 32, Processing Time 0.022 seconds

Size-Reduced Ring-Hybrid Coupler Using Phase-Inverting Ultra-Wideband Transitions and Its Frequency Doubler Application (초광대역 위상 역전 전이 구조를 이용한 소형화된 링 하이브리드 결합기 및 주파수 체배기 응용)

  • Song, Sun-Young;Kim, Young-Gon;Park, Jin-Hyun;Kim, Kang-Wook
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.21 no.9
    • /
    • pp.1037-1044
    • /
    • 2010
  • In this paper, a new size-reduced, wideband ring-hybrid coupler is presented, and a design of a planar single-balanced doubler using the ring-hybrid is shown. This ring-hybrid coupler employs a pair of ultra-wideband transitions for phase inversion, which consists of in-phase and out of-phase transitions providing a good amplitude and phase balances for wide frequency ranges. The implemented ring-hybrid is 65 % smaller than conventional ring-hybrids, and provides 92.5 % and 81.3 % bandwidth at $\sum$ and $\Delta$ ports, respectively. Thanks to good amplitude and phase balances over wide bandwidth, the ring-hybrid can be applied to implement various balanced components. The implemented single-balanced doubler utilizing the ring-hybrid exhibits typical conversion loss of 10.5 dB for the output frequency range of 4~12 GHz with fundamental suppression level of 30 dB. The performance was also well-predicted with the nonlinear circuit simulation.

Design of 2-Ch DC-DC Converter with Wide-Input Voltage Range of 2.9V~5.6 V for Wearable AMOLED Display (2.9V~5.6V의 넓은 입력 전압 범위를 가지는 웨어러블 AMOLED용 2-채널 DC-DC 변환기 설계)

  • Lee, Hui-Jin;Kim, Hak-Yun;Choi, Ho-Yong
    • Journal of IKEEE
    • /
    • v.24 no.3
    • /
    • pp.859-866
    • /
    • 2020
  • This paper proposes a 2-ch DC-DC converter with a wide-input voltage range from 2.9V~5.6V for wearable AMOLED displays. For positive voltage VPOS, a boost converter is designed using an over-charged voltage permissible circuit (OPC) which generates a normal output voltage even if over-input voltage is applied, and a SPWM-PWM dual mode with 3-segmented power transistors to improve efficiency at light load. For negative voltage VNEG, a 0.5x regulated inverting charge pump is designed to increase power efficiency. The proposed DC-DC converter was designed using a 0.18-㎛ BCDMOS process. Simulation results show that the proposed DC-DC converter generates VPOS voltages of 4.6 V and VNEG voltage of -0.6V~-2.3V for input voltage of 2.9V to 5.6V. In addition, it has power efficiency of 49%~92%, output ripple voltage has less than 20 mV for load current range of 1 mA~70 mA.