• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.4
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• pp.361-367
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• 2014

This paper is related to a new solar power conditioner for a built-in step-up chopper function. In the first step-up chopper proposed solar PV power conditioner for mutually connected in series with the input voltage of the bypass diodes are respectively connected to the positive terminal should install the mutual boosting chopper diode connected in series with the boost chopper switching element between the two power supply and at the same time the first and the second was connected to a second diode and a resonance inductor and a snubber capacitor in series with each other. And the common connection point between the bypass diode and the step-up chopper and the step-up chopper diode common connection point of the switching elements of the input voltage was set to the boost inductor for storing energy. In addition, between the step-up chopper and the step-up chopper diode and a switching element of a joint connection point of the first auxiliary diode and the second common connection point of the auxiliary diode was provided, the resonance capacitor. Between the step-up chopper and the step-up chopper diode and a switching element of a joint connection point and the common connection point of the resonance inductor snubber capacitor and connecting the third secondary diode, between two power supply lines is characterized by configuring the DC link capacitor bus lines in parallel. Therefore, it is possible to suppress the switching loss through, DC link bus lines, as well as there could seek miniaturization and weight reduction of the power conditioner itself by using a common capacitor of the non-polar non-polar electrolytic capacitor having a capacitor, the service life of the circuit can be extended and it is possible to greatly reduce the loss can be greatly improve the reliability of the product and the operation of the product itself.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Electrical & Electronic Materials
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• v.9 no.1
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• pp.30-37
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• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.4
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• pp.278-286
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• 2008

This paper investigates the fault generation type and the cause of output interruptionsin bulky with $30^{\sim}500[KVA]$ double conversion UPS, and proposes the fault detection method to improve the reliability of power supply used in the critical load in industry. Identifies its existing way of detecting a quality of inverter output it to bypass when exceeds its expectation. Under a UPS managing system, when an inner (Power device, Controller, CPU) fault occurs it disrupts the power supply and these occurrences has been verified by the results of experiments and application results. To overcome these problems, the proposed method constructs independently a fault-detection, a bypass-control device and a triple power supply apart from the conventional UPS operation. Also the detection point is changed to the preceding of a circuit breaker, a reference of fault detection is modified to avoid any clash and the breaking equipment is attached to intercept a spread of accident. As a result of applications of these developed systems to 242 UPS which was installed purposefully to the communication power supply, the service errors has not occurred in the UPS for two years since 2006.

• Journal of Power Electronics
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• v.19 no.4
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• pp.922-933
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• 2019

The arm inductance (AI) of a modular multilevel converter (MMC) affects both the fault and circulating current magnitudes. In addition, it has an impact on the inverter efficiency and harmonic content. In this study, the AI of a three-phase MMC is optimized in a novel way in terms of DC voltage utilization, harmonics and efficiency. This MMC has 10 submodules (SM) per arm and the power circuit topology of the SM is a half-bridge. The optimum AI is adopted and verified in an MMC that has 100 SMs per arm. Then the phase shift (PS) and phase disposition (PD) pulse width modulation (PWM) methods are investigated for better DC voltage utilization, efficiency and harmonics. It is found that similar performances are obtained for both modulation techniques in terms of DC voltage utilization. However, the total harmonic distortion (THD) of the PS-PWM is found to be 0.02%, which is slightly lower than the THD of the PD-PWM at 0.16%. In efficiency calculations, the switching and conduction losses for all of the semiconductor are considered separately and the minimum efficiency of the 100-SM based MMC is found to be 99.62% for the PS-PWM and 99.64% for the PD-PWM with the optimal value of the AI. Simulation results are verified with an experimental prototype of a 6-SM based MMC.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.3
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• pp.129-135
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• 2021

Switched Reluctance Motor (SRM) has a characteristic that the inductance changes very nonlinearly depending on the magnitude of the current and the relative position of the rotor and stator, and the torque is generated In consideration of these problems, many studies have been conducted on a topology for driving that can improve efficiency and performance in an existing asymmetric bridge converter in order to simplify the circuit and economic efficiency. Therefore, in this paper, we want to check the performance by comparing and analyzing each converter used by applying it as a topology for SRM driving. The driving converters applied to the comparison and analysis are Conventional C-dump, Modified C-dump, Energy efficient C-dump, Resonant C-dump converter with C-dump converter type structure and the most widely used asymmetric bridge converter and 6-Switch inverter that used for general motors.

• The Journal of the Korea Contents Association
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• v.21 no.6
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• pp.44-50
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• 2021

In this paper, we analyze the efficiency of light sources of CCFL and LED monitors. Cold Cathode Fluorescent Lamp (CCFL), which is widely used as a light source for LCD display, supplies a high voltage of 1,200[V] or more when it is initially driven. In addition, a constant normal voltage of 400 ~ 800[V] after lighting, and 3 ~ 6[ mA] is needed for a power circuit that can stabilize the current. Applying a high voltage causes a lot of stress on the inverter and generates a lot of heat in the cold cathode lamp, causing significant damage to the BLU (Back Light Unit), resulting in a burning phenomenon, which causes the screen to output normal colors when outputting the screen. We can not see the yellow output and the screen darkened. Therefore, in order to prevent such a symptom in advance, efficiency can be increased by using a Light Emitting Diode (LED) as the light source of the LCD display instead of a cold cathode fluorescent lamp (CCFL). As a result, it is shown that the LED method outperforms the CCFL method.

• Proceedings of the KIPE Conference
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• 2009.11a
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• pp.105-110
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• 2009

The On Line Electric Vehicles(OLEV) that can pick up inductive power from underground coils on driving with high efficiency have been developed this year, and is now proposed in this paper. The IPS(Inductive Power Supply) system consists of power supply inverters, power supply rails, pick up modules, and a regulator. There are 3 generations of IPS have been developed so far, and the $4^{th}$ generation IPS is being developed. The $1^{st}$ generation has been demonstrated this Feb. 27, which is equipped with mechanically auto tracking pick-up module with 1cm air gap, and showed 80% power efficiency. The $2^{nd}$ generation IPS applied to an 120kW (average)/240kW(peak) motor powered electric bus has 17cm air gap with 72% power efficiency. For the $2^{nd}$ generation IPS, the Power supply inverter has 440V, 3phase input and 200A @ 20kHz output. The test power supply rail of 240m long is segmented by 60m each, where newly developed core structure and power cable are constructed under the road covered with asphalt of 5cm thickness. The pick-up modules which consist of core, winding wire, and rectifiers are fixed to the bottom of the bus which can carry more than 40 passengers and can pick up max. 60kW. To remove parasitic component and to transfer maximum power between them resonant circuit topology is applied to the primary and secondary sides. The EMF level is below 62.5mG at 1.75m from the center of the road to meet the regulation. Several effective ways of reducing EMF levels have been developed. In addition, effective ways to solve problems related high frequency power cables buried in ground and it's proof from soil have been studied also. This development shows that the IPS system is capable of supplying enough power to the pick-up of OLEV and can reduce battery size, weight and cost, which means the IPS with OLEV is one of the best candidate for EV.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.1
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• pp.70-79
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• 2003

In this paper, T5 28-watt fluorescent lamp ballast using a piezoelectric transformer is fabricated and its characteristic is investigated. Developed electronic ballast is composed of basic circuits and blocks, such as rectifier part, active power factor corrector part, frequency oscillation part using microcontroller and feedback control, piezoelectric transformer and resonant half bridge inverters. The fabricated ballast uses to variable frequency methode in external so exciting that the frequency of piezoelectric transformer could be generated by voltage control oscillator using microcontroller(AT90S4433). The current of fluorescent lamp is detected by feedback control circuit. The signal of inverter output is received using Piezoelectric transformer, and then its output transmitted to fluorescent lamp. Traditional electromagnetic ballasts operated at 50-60Hz have been suffered from noticeable flicker, high loss, large crest factor and heavy weight. A new electronic ballast is operated at high frequency about 75kHz, and then Input power factor, distortion of total harmonic and lamp current crest factor are measured about 0.9!35, 12H and 1.5, respectively Accordingly, the traditional ballast is by fabricated electronic ballast using piezoelectric transformer and voltage control oscillator because of its lighter weight, high efficiency, economic merit and saving energy.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.