• Title/Summary/Keyword: Inverter Circuit

Search Result 1,222, Processing Time 0.031 seconds

The Speed Control of a Single-sided Linear Induction Motor for the Automatic Conveyor system (자동 반송 시스템용 SLIM의 속도제어)

  • Jeong, B.C.;Cho, Y.H.;Lee, O.G.;Shin, D.R..;Woo, J.I.
    • Proceedings of the KIEE Conference
    • /
    • 1995.07a
    • /
    • pp.285-287
    • /
    • 1995
  • In the case of driving the SLIM(Single-sided Linear Induction Motor) as the VVVF inverter, the performance of SLIM, which is a thrust, normal force and so on, varies according to a slip frequency as a function of the external load. It is impossible that the open-loop control method control the speed of a SLIM accurately. So that, this paper is proposed the speed control method of a SLIM for a automatic conveyor system with the slip frequency vector control method. To analyze the dynamic characteristics of a SLIM, the state equation is derived from the equivalent circuit of the SLIM, ignored the end effect. The slip frequency and the normal force of SLIM are constantly controlled at the steady state. The simulated results is compared with the experimental values.

  • PDF

Design and Analysis of Universal Power Converter for Hybrid Solar and Thermoelectric Generators

  • Sathiyanathan, M.;Jaganathan, S.;Josephine, R.L.
    • Journal of Power Electronics
    • /
    • v.19 no.1
    • /
    • pp.220-233
    • /
    • 2019
  • This work aims to study and analyze the various operating modes of universal power converter which is powered by solar and thermoelectric generators. The proposed converter is operated in a DC-DC (buck or boost mode) and DC-AC (single phase) inverter with high efficiency. DC power sources, such as solar photovoltaic (SPV) panels, thermoelectric generators (TEGs), and Li-ion battery, are selected as input to the proposed converter according to the nominal output voltage available/generated by these sources. The mode of selection and output power regulation are achieved via control of the metal-oxide semiconductor field-effect transistor (MOSFET) switches in the converter through the modified stepped perturb and observe (MSPO) algorithm. The MSPO duty cycle control algorithm effectively converts the unregulated DC power from the SPV/TEG into regulated DC for storing energy in a Li-ion battery or directly driving a DC load. In this work, the proposed power sources and converter are mathematically modelled using the Scilab-Xcos Simulink tool. The hardware prototype is designed for 200 W rating with a dsPIC30F4011 digital controller. The various output parameters, such as voltage ripple, current ripple, switching losses, and converter efficiency, are analyzed, and the proposed converter with a control circuit operates the converter closely at 97% efficiency.

Channel and Gate Workfunction-Engineered CNTFETs for Low-Power and High-Speed Logic and Memory Applications

  • Wang, Wei;Xu, Hongsong;Huang, Zhicheng;Zhang, Lu;Wang, Huan;Jiang, Sitao;Xu, Min;Gao, Jian
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.16 no.1
    • /
    • pp.91-105
    • /
    • 2016
  • Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

4-Channel 2.5-Gb/s/ch CMOS Optical Receiver Array for Active Optical HDMI Cables (액티브 광케이블용 4-채널 2.5-Gb/s/ch CMOS 광 수신기 어레이)

  • Lee, Jin-Ju;Shin, Ji-Hye;Park, Sung-Min
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.49 no.8
    • /
    • pp.22-26
    • /
    • 2012
  • This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.

A Study on Power Conversion System for Fuel Cell Controlled by Micro-Processor (마이크로프로세서에 의해 제어되는 연료전지용 전력변환장치에 관한 연구)

  • Kim, Ju-Yong;Jung, Sang-Hwa;Mun, Sang-Pil;Ryu, Jae-Yup;Suh, Ki-Young
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
    • /
    • v.21 no.5
    • /
    • pp.10-24
    • /
    • 2007
  • In the dissertation, a power conversion system for fuel cell is composed of a PWM inverter with LC filter in order to convert fuel cell voltage to a single phase 220[V]. In addition, new insulated DC-DC converters are proposed in order that fuel cell voltage is boosted to 380[V]. In this paper, it requires smaller components than existing converters, which makes easy control. The proposed DC-DC converter controls output power by the adjustment of phase-shift width using switch $S_5\;and\;S_6$ in the secondary switch which provides 93-97[%] efficiency in the wide range of output voltage. Fuel cell simulator is implemented to show similar output characteristics to actual fuel cell. Appropriate dead time td enables soft switching to the range where the peak value of excitation current in a high frequency transformer is in accordance with current in the primary circuit. Moreover, appropriate setting to serial inductance La reduces communication loss arisen at light-load generator and serge voltage arisen at a secondary switch and serial diode. Finally, TMS320C31 board and EPLD using PWM switching technique to act a single phase full-bridge inverter which is planed to make alternating current suitable for household

Evaluation and Experimental Production of Single-Phase Full-wave Rectification Type for X-ray Equipment of High Precision (고정밀도의 단상전파정류형 X선 장치의 제작 및 평가)

  • Han, Dong-Kyoon;Jung, Jae-Eun;Choi, Jun-Gu;Seoun, Youl-Hun;Ko, Shin-Gwan
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.12 no.1
    • /
    • pp.413-419
    • /
    • 2011
  • Diagnosis X-ray equipment localized at 1950's but it is developed suddenly at 1960's with demand together. Manufacture of Diagnostic X-ray equipment is controled by the KS regulation and the Ministry of Health and Welfare because of hazardous element etc. exposure by radiation. Most of diagnostic X-ray equipment ware single phase and three phase full-wave rectification but from 1980's it transforms it was exchanged in inverter type X-ray equipment. Inverter type X-ray equipment produces approximately 50~80% more average photon intensity then single phase full-wave rectification and the accuracy is high. But from a clinic it dose not use because expensive therefor the efficiency improvement of single phase full-wave rectification is necessary. We produced single phase full-wave rectification X-ray equipment control unit, high tension transformer, filament heating transformer, rectification circuit, high tension cable and others and evaluated efficiency, in result which is excellent compare with Rule of Safety Management and KS regulation.

A 12Bit 80MHz CMOS D/A Converter with active load inverter switch driver (능동부하 스위치 구동 회로를 이용한 12비트 80MHz CMOS D/A 변환기 설계)

  • Nam, Tae-Kyu;Seo, Sung-Uk;Shin, Sun-Hwa;Joo, Chan-Yang;Kim, Soo-Jae;Lee, Sang-Min;Yoon, Kwang-S.
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.44 no.8
    • /
    • pp.38-44
    • /
    • 2007
  • This paper describes a 12 bit 80MHz CMOS D/A converter for wireless transceiver. Proposed circuit in the paper employes segmented structure which consists of four stage 3bit thermometer decoders. Proposed D/A converter is manufactured 0.35um CMOS n-well digital standard process and measurement results show a ${\pm}1.36SB/{\pm}0.62LSB$ of INL/DNL and $46pV{\cdot}s$ of glitch energy. SNR and SFDR are measured to be 58.5dB and 64.97dB @ Fs=80MHz and Fin=19MHz with a total power consumption of 99mW. Such results proved that our work has low power consumption, high linearity, low glitch and improved dynamic performance. Therefore, our work can be appled to various high speed and high performance circuits.

Development of 1.2[kW]Class Fuel Cell Power Conversion System (1.2[kW]급 연료전지용 전력변환장치의 개발)

  • Suh, Ki-Young;Kim, Chil-Ryong;Cho, Man-Chul;Kim, Jung-Do;Yoon, Young-Byun;Kim, Hong-Sin;Park, Do-Hyung;Ha, Sung-Hyun
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
    • /
    • v.21 no.6
    • /
    • pp.117-125
    • /
    • 2007
  • Recently, a fuel cell with low voltage and high current output characteristics is remarkable for new generation system. It needs both a DC-DC step-up converter and DC-AC inverter to be used in fuel cell generation system. Therefor, this paper, consists of an isolated DC-DC converter to boost the fuel cell voltage 380[VDC] and a PWM inverter with LC filter to convent the DC voltage to single-phase 220[VAC]. Expressly, The fuel cell system which it proposes DC-DC the efficient converter used PWM the phase transient control law and it depended to portion resonance ZVS switching, loss peek voltage and electric current of realization under make schedule, switching frequency anger and the switch reduction. And mind benevolence it sprouted 2 in stop circuit and it added and a direct current voltage and the electric current where the ingredient is reduced in load side ripple stable under make whom it will be able to supply. Besides the efficiency of 92[%]is obtained over the wide output voltage regulation ranges and load variations. Also, under make over together the result leads simulation and test, the propriety confirmation.

Total Simulation for the Noise Prediction of Motor Driving System in EV/HEV System (EV/HEV용 모터 구동 시스템의 Noise 예측을 위한 통합 시뮬레이션에 대한 연구)

  • Gwon, O-Hyun;Lee, Jae Joong;Kim, Kwang-Ho;Ahn, Ji-Hyun;Kweon, Hyuck-Su;Kim, Mi-Ro;Jung, Sang-Yong;Nah, Wansoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.24 no.7
    • /
    • pp.710-721
    • /
    • 2013
  • The noise prediction of motor driving system is one of the most important parts in EV/HEV, as the number of power electronic devices increases. This paper describes the mechanism of noise making process and proposes a simulation model of motor driving system for the prediction of the conducted noise. Theoretical calculations and model based simulations were carried out. DOD-dependent-battery parameters were extracted by AC analysis, and an inverter model including dynamic diode was used. Furthermore, 2-D EM tool was used for the motor modeling and was combined with the circuit models of battery and inverter. The simulated voltages, currents and spectrums in the motor driving system showed qualitatively meaningful results, suggesting the validness of the suggested modeling methods.

Simulation Study of a Large Area CMOS Image Sensor for X-ray DR Detector with Separate ROICs (센서-회로 분리형 엑스선 DR 검출기를 위한 대면적 CMOS 영상센서 모사 연구)

  • Kim, Myung Soo;Kim, Hyoungtak;Kang, Dong-uk;Yoo, Hyun Jun;Cho, Minsik;Lee, Dae Hee;Bae, Jun Hyung;Kim, Jongyul;Kim, Hyunduk;Cho, Gyuseong
    • Journal of Radiation Industry
    • /
    • v.6 no.1
    • /
    • pp.31-40
    • /
    • 2012
  • There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.