• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.1034-1037
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• 2003

Microcrystalline silicon(c-Si:H) thin-film solar cells are prepared with intrinsic Si-layer by hot wire CVD. The operating parameters of solar cells are strongly affected by the filament temperature ($T_f$) during intrinsic layer. Jsc and efficiency abruptly decreases with elevated $T_f$ to $1400^{\circ}C$. This deterioration of solar cell parameters are resulted from increase of crystalline volume fraction and corresponding defect density at high $T_f$. The heater temperature ($T_h$) are also critical parameter that controls device operations. Solar cells prepared at low $T_h$ ($<200^{\circ}C$) shows a similar operating properties with devices prepared at high $T_f$, i.e. low Jsc, Voc and efficiency. The origins for this result, however, are different with that of inferior device performances at high $T_f$. In addition the phase transition of the silicon films occurs at different silane concentration (SC) by varying filament temperature, by which highest efficiency with SC varies with $T_f$.

• Current Photovoltaic Research
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• 제1권2호
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• pp.73-81
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• 2013

Heterojunction with Intrinsic Thin-layer (HIT) solar cells are currently an important subject in industrial trends for thinner solar cell wafers due to the low-temperature of production processes, which is around $200^{\circ}C$, and due to their high-efficiency of 24.7%, as reported by the Panasonic (Sanyo) group. The use of thinner wafers and the enhancement of cell performance with fabrication at low temperature have been special interests of the researchers. The fundamental understanding of the band bending structures, choice of materials, fabrication process, and nano-scale characterization methods to provide necessary understanding of the interface passivation mechanisms, emitter properties, and requirements for transparent oxide conductive layers is presented in this review. This information should be used for the performance characterization of the developing technologies for HIT solar cells.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 C
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• pp.1598-1600
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• 2003

Microcrystalline silicon(c-Si:H) thin-film solar cells are prepared with intrinsic Si-layer by hot wire CVD. The operating parameters of solar cells are strongly affected by the filament temperature ($T_f$) during intrinsic layer. Jsc and efficiency abruptly decreases with elevated $T_f$ to $1400^{\circ}C$. This deterioration of solar cell parameters are resulted from increase of crystalline volume fraction and corresponding defect density at high $T_f$ The heater temperature ($T_h$) are also critical parameter that controls device operations. Solar cells prepared at low $T_h$ (<$200^{\circ}C$) shows a similar operating properties with devices prepared at high $T_f$, i.e. low Jsc, Voc and efficiency. The origins for this result, however, are different with that of inferior device performances at high $T_f$. In addition the phase transition of the silicon films occurs at different silane concentration (SC) by varying filament temperature, by which highest efficiency with SC vanes with $T_f$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.659-659
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• 2013

Recently, graphene has been intensively studied due to the fascinating physical, chemical and electrical properties. It shows high carrier mobility, high current density, and high thermal conductivity compare with conventional semiconductor materials even it has single atomic thickness. Especially, since graphene has fantastic electrical properties many researchers are believed that graphene will be replacing Si based technology. In order to realize it, we need to prepare the large and uniform graphene. Chemical vapor deposition (CVD) method is the most promising technique for synthesizing large and uniform graphene. Unfortunately, CVD method requires transfer process from metal catalyst. In transfer process, supporting polymer film (Such as poly (methyl methacrylate)) is widely used for protecting graphene. After transfer process, polymer layer is removed by organic solvents. However, it is impossible to remove it completely. These organic residues on graphene surface induce quality degradation of graphene since it disturbs movement of electrons. Thus, in order to get an intrinsic property of graphene completely remove of the organic residues is the most important. Here, we introduce modified wet graphene transfer method without PMMA. First of all, we grow the graphene from Cu foil using CVD method. And then, we deposited several metal films on graphene for transfer layer instead of PMMA. Finally, we fabricate graphene FET devices. Our approaches show low defect density and non-organic residues in comparison with PMMA coated graphene through Raman spectroscopy, SEM and AFM. In addition, clean graphene FET shows intrinsic electrical characteristic and high carrier mobility.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.280.2-280.2
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• 2016

The graphene, a single atomic sheet of graphite, has attracted tremendous interest owing to its novel properties including high intrinsic mobility, optical transparency and flexibility. However, for more diverse application of graphene devices, it is essential to tune its transport behavior by shifting Dirac Point (DP) of graphene. So, in the following context, we suggest a method to tune structural and electronic properties of graphene using atomic layer deposition. By atomic layer deposition of zinc oxide (ZnO) on graphene using 4-mercaptophenol as linker, we can fabricate n-doped graphene. Through ${\pi}-{\pi}$ stacking between chemically inert graphene and 4-mercaptophenol, conformal deposition of ZnO on graphene was enabled. The electron mobility of graphene TFT increased more than 3 times without considerably decreasing the hole mobility, compared to the pristine graphene. Also, it has high air stability. This ZnO doping method by atomic layer deposition can be applicable to large scale array of CVD graphene TFT.

• International Journal of Concrete Structures and Materials
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• 제8권4호
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• pp.269-278
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• 2014

When concrete is being transported through a pipe, the lubrication layer is formed at the interface between concrete and the pipe wall and is the major factor facilitating concrete pumping. A possible mechanism that illustrates to the formation of the layer is the shear-induced particle migration and determining the rheological parameters is a paramount factor to simulate the concrete flow in pipe. In this study, numerical simulations considering various rheological models in the shear-induced particle migration were conducted and compared with 170 m full-scale pumping tests. It was found that the multimodal viscosity model representing concrete as a three-phase suspension consisting of cement paste, sand and gravel can accurately simulate the lubrication layer. Moreover, considering the particle shape effects of concrete constituents with increased intrinsic viscosity can more exactly predict the pipe flow of pumped concrete.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.491.2-491.2
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• 2014

Generally, silicon heterojunction solar cell has intrinsic and n-type of hydrogenated amorphous silicon (a-Si:H) as passivation layer and BSF layer. In this study, antimony, novel material, deposited on back side of the heterojunction solar cell as passivation and BSF layer to substitute the a-Si:H and the characteristics of the solar cell such electrical properties and optical properties were analyzed. And SIMS analysis was carried out to obtain the depth profile of the BSF layer which was deposited by laser annealing process.

• ETRI Journal
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• 제35권4호
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• pp.730-733
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• 2013

In this work, buffer layers with various conditions are inserted at an n/i interface in hydrogenated amorphous silicon semitransparent solar cells. It is observed that the performance of a solar cell strongly depends on the arrangement and thickness of the buffer layer. When arranging buffer layers with various bandgaps in ascending order from the intrinsic layer to the n layer, a relatively high open circuit voltage and short circuit current are observed. In addition, the fill factors are improved, owing to an enhanced shunt resistance under every instance of the introduced n/i buffer layers. Among the various conditions during the arrangement of the buffer layers, a reverse V shape of the energy bandgap is found to be the most effective for high efficiency, which also exhibits intermediate transmittance among all samples. This is an inspiring result, enabling an independent control of the conversion efficiency and transmittance.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.480.1-480.1
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• 2014

In this study, we suggest the new emitter formation applied solid phase epitaxy (SPE) growth process using rapid thermal process (RTP). Preferentially, we describe the SPE growth of intrinsic a-Si thin film through RTP heat treatment by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD). Phase transition of intrinsic a-Si thin films were taken place under $600^{\circ}C$ for 5 min annealing condition measured by spectroscopic ellipsometer (SE) applied to effective medium approximation (EMA). We confirmed the SPE growth using high resolution transmission electron microscope (HR-TEM) analysis. Similarly, phase transition of P doped a-Si thin films were arisen $700^{\circ}C$ for 1 min, however, crystallinity is lower than intrinsic a-Si thin films. It is referable to the interference of the dopant. Based on this, we fabricated 16.7% solar cell to apply emitter layer formed SPE growth of P doped a-Si thin films using RTP. We considered that is a relative short process time compare to make the phosphorus emitter such as diffusion using furnace. Also, it is causing process simplification that can be omitted phosphorus silicate glass (PSG) removal and edge isolation process.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2006년도 춘계학술대회
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• pp.214-217
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• 2006

p-type 비정질 실리콘 에미터와 n-type 실리콘 기판의 계면에 intrinsic 비정질 실리콘을 증착함으로써 계면의 재결합을 억제하여 20%가 넘는 효율을 보이는 이종접합 태양전지가 Sanyo에 의해 처음 제시된 후 intrinsic layer에 대한 연구가 많이 진행되어 왔다. 하지만 p-type wafer의 경우는 n-type에 비해 intrinsic buffer의 효과가 미미하거나 오히려 특성을 저하시킨다는 보고가 있으며 그 이유로는 minority carrier에 대한 barrier가 상대적으로 낮다는 것과 partial epitaxy가 발생하기 때문으로 알려져 있다. 본 연구에서는 partial epitaxy를 억제하기 위한 방법으로 증착 온도를 낮추고 QSSPC를 사용하여 minority carrier lifetime을 측정함으로써 각 온도에 따른 passivation 특성을 평가하였다. 또한 SiH4에 H2를 섞어서 증착하였을 경우 각 dilution ratio(H2 flow/SiH4 flow)에서의 passivation 특성 또한 평가하였다. 기판 온도 $100^{\circ}C$에서 증착된 샘플의 lifetime이 가장 길었으며 그 이하와 이상에서는 lifetime이 감소하는 경향을 보였다 낮은 온도에서는 박막 자체의 결함이 증가하였기 때문이며 높은 온도에서는 partial epitaxy의 영향으로 추정된다. H2 dilution을 하여 증착한 샘플의 경우 SiH4만 가지고 증착한 샘플보다 훨씬 높은 lifetime을 가졌다 이 또한 박막 FT-IR결과로부터 H2 dilution을 한 경우 compact한 박막이 형성되는 것을 확인할 수 있었는데 radical mobility 증가에 의한 박막 특성 향상이 원인으로 생각된다.