• Title/Summary/Keyword: Internal Fault

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Hybrid metrics model to predict fault-proneness of large software systems (대형 소프트웨어 시스템의 결함경향성 예측을 위한 혼성 메트릭 모델)

  • Hong, Euy-Seok
    • The Journal of Korean Association of Computer Education
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    • v.8 no.5
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    • pp.129-137
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    • 2005
  • Criticality prediction models that identify fault-prone spots using system design specifications play an important role in reducing development costs of large systems such as telecommunication systems. Many criticality prediction models using complexity metrics have been suggested. But most of them need training data set for model training. And they are classification models that can only classify design entities into fault-prone group and non fault-prone group. To solve this problem, this paper builds a new prediction model, HMM, using two styled hybrid metrics. HMM has strong point that it does not need training data and it enables comparison between design entities by criticality. HMM is implemented and compared with a well-known prediction model, BackPropagation neural network Model(BPM), considering internal characteristics and accuracy of prediction.

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A Study on the Fault Detection of ASIC using Dynamic Pattern Method (Dynamic Pattern 기법을 이용한 주문형 반도체 결함 검출에 관한 연구)

  • Shim, Woo-Che;Jung, Hae-Sung;Kang, Chang-Hun;Jie, Min-Seok;Hong, Gyo-Young;Ahn, Dong-Man;Hong, Seung-Beom
    • Journal of Advanced Navigation Technology
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    • v.17 no.5
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    • pp.560-567
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    • 2013
  • In this paper, it is proposed the fault detection method of the ASIC, without the Test Requirement Document(TRD), extracting internal logic circuit and analyzed the function of the ASIC using the multipurpose development program and simulation. If there don't have the TRD, it is impossible to analyze the operation of the circuit and find out the fault detection in any chip. Therefore, we make the TRD based on the analyzed logic data of the ASIC, and diagnose of the ASIC circuit at the gate level through the signal control of I/O pins using the Dynamic Pattern signal. According to the experimental results of the proposed method, we is confirmed the good performance of the fault detection capabilities which applied to the non-memory circuit.

The Software Reliability Evaluation of a Nuclear Controller Software Using a Fault Detection Coverage Based on the Fault Weight (가중치 기반 고장감지 커버리지 방법을 이용한 원전 제어기기 소프트웨어 신뢰도 평가)

  • Lee, Young-Jun;Lee, Jang-Soo;Kim, Young-Kuk
    • KIPS Transactions on Computer and Communication Systems
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    • v.5 no.9
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    • pp.275-284
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    • 2016
  • The software used in the nuclear safety field has been ensured through the development, validation, safety analysis, and quality assurance activities throughout the entire process life cycle from the planning phase to the installation phase. However, this evaluation through the development and validation process needs a lot of time and money, and there are limitations to ensure that the quality is improved enough. Therefore, the effort to calculate the reliability of the software continues for a quantitative evaluation instead of a qualitative evaluation. In this paper, we propose a reliability evaluation method for the software to be used for a specific operation of the digital controller in a nuclear power plant. After injecting weighted faults in the internal space of a developed controller and calculating the ability to detect the injected faults using diagnostic software, we can evaluate the software reliability of a digital controller in a nuclear power plant.

A Software Quality Prediction Model Without Training Data Set (훈련데이터 집합을 사용하지 않는 소프트웨어 품질예측 모델)

  • Hong, Euy-Seok
    • The KIPS Transactions:PartD
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    • v.10D no.4
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    • pp.689-696
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    • 2003
  • Criticality prediction models that determine whether a design entity is fault-prone or non fault-prone are used for identifying trouble spots of software system in analysis or design phases. Many criticality prediction models for identifying fault-prone modules using complexity metrics have been suggested. But most of them need training data set. Unfortunately very few organizations have their own training data. To solve this problem, this paper builds a new prediction model, KSM, based on Kohonen SOM neural networks. KSM is implemented and compared with a well-known prediction model, BackPropagation neural network Model (BPM), considering internal characteristics, utilization cost and accuracy of prediction. As a result, this paper shows that KSM has comparative performance with BPM.

D-q Equivalent Circuit-based Protection Algorithm for a Doubly-fed Induction Generator in the Time Domain

  • Kang, Yong-Cheol;Kang, Hae-Gweon;Lee, Ji-Hoon
    • Journal of Electrical Engineering and Technology
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    • v.5 no.3
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    • pp.371-378
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    • 2010
  • Most modern wind turbines employ a doubly-fed induction generator (DFIG) system due to its many advantages, such as variable speed operation, relatively high efficiency, and small converter size. The DFIG system uses a wound rotor induction machine so that the magnetizing current of the generator can be fed from both the stator and the rotor. We propose a protection algorithm for a DFIG based on a d-q equivalent circuit in the time domain. In the DFIG, the voltages and currents of the rotor side and the stator side are available. The proposed algorithm estimates the instantaneous induced voltages of magnetizing inductance using those voltages and currents from both the stator and the rotor sides. If the difference between the two estimated induced voltages exceeds the threshold, the proposed algorithm detects an internal fault. The performance of the proposed algorithm is verified under various operating and fault conditions using a PSCAD/EMTDC simulator.

Hardware implementation and error analysis of an algorithm for compensating the secondary current of iron-cored current transformers (철심 변류기의 2차 전류 보상 알고리즘의 실시간 구현 및 오차 분석)

  • 강용철;김성수;박종근;강상희;김광호
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.45 no.4
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    • pp.490-500
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    • 1996
  • The conventional method to deal with current transformer (CT) Saturation is over dimensioning of the core so that CTs can carry up to 20 times the rated current without exceeding 10% ratio correction. However, this not only reduces the sensitivity of relays as some errors may still be present in the secondary current when a severe fault occurs, but also increases the CT size. This paper presents an algorithm for compensating the distorted secondary current of iron-cored CTs under CT saturation using the magnetization (flux-current : .lambda.-i) curve and its performance is examined for fault currents encountered on a typical 345[kV] Korean transmission system, under a variety of different system and fault conditions. In addition, the results of hardware implementation of the algorithm using a TMS320C10 digital signal processor are also presented. The proposed algorithm can improve the sensitivity of relays to low level internal faults, maximize the stability of relays for external faults, and reduce the required CT core cross-section significantly. (author). refs., figs.

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Model-based Analysis of Cell-to-Cell Imbalance Characteristic Parameters in the Battery Pack for Fault Diagnosis and Over-discharge Prognosis (배터리 팩 내부 과방전 사전 진단을 위한 모델기반 셀 간 불균형 특성 파라미터 분석 연구)

  • Park, Jinhyeong;Kim, Jaewon;Lee, Miyoung;Kim, Byoung-Choul;Jung, Sung-Chul;Kim, Jonghoon
    • The Transactions of the Korean Institute of Power Electronics
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    • v.26 no.6
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    • pp.381-389
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    • 2021
  • Most diagnosis approaches rely on historical failure data that might not be feasible in real operating conditions because the battery voltage and internal parameters are nonlinear according to various operating conditions, such as cell-to-cell configuration and initial condition. To overcome this issue, the estimator and the predictor require integrated approaches that consider comprehensive data, with the degradation process and measured data taken into account. In this paper, vector autoregressive models (VAR) with various parameters that affect overdischarge to the cell in the battery pack were constructed, and the cell-to-cell parameters were identified using an adaptive model to analyze the influence of failure prognosis. The theoretical analysis is validated using experimental results in terms of the feasibility and advantages of fault prognosis.

A Fault Simulator for IDDQ Testing (IDDQ 테스트를 위한 고장 시뮬레이터)

  • 배성환;김대익;이창기;전병실
    • The Journal of the Acoustical Society of Korea
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    • v.18 no.1
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    • pp.92-96
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    • 1999
  • As CMOS technologies have been rapidly developed, bridging faults have been relatively increased. IDDQ testing is a current testing methodology which can enhance reliability of the circuit since it efficiently detects bridging faults that are difficult to detect by functional testing. In this paper we consider internal bridging faults occurred in each gate of logic circuits under test and finally develop a fault simulator for IDDQ testing to detect assumed bridging faults.

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Lift-Off Voltage and Partial Discharge Characteristics of Free Metallic Particles in GIS (GIS 내 금속입자의 부상전압과 부분방전특성 연구)

  • Yun, Jin-Yeol;Han, Sang-Ok
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.48 no.2
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    • pp.127-132
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    • 1999
  • Both motion of free metallic particles from which most GIS internal failures are caused and partial discharges from the particles were examined using EHV GIS test chamber. Effects from particle length and gas pressure which are main factors to lead to breakdown failure were investigated theoretically and experimentally. Magnitude of both lift-off voltage and partial discharge inception voltage were measured respectively and, through these measurements, this paper showed the possibility of predicting breakdown fault and of taking action to prevent the fault in advance. The measurement of partial discharge when the particles began to move could be adopted to decide minimum sensitivity in developing predictive diagnostic equipments. Both the amount of apparent discharge and real discharge in GIS were examined theoretically and experimentally, then experimental results were analyzed on the basis of the theory.

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Test Time Reduction of BIST Using Internal Nodes of a Circuit (회로 내부 노드를 이용한 BIST의 테스트 시간 감소)

  • 최병구;장윤석;김동욱
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.397-400
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    • 1999
  • As the result of enhancement of CAD, Design Automation and manufacturing technology, it's on the increasing complexity, integration ratio, data signals, and pin count to IC chips. This brings about difficulties of testing, and incresing test time. Now One of the most cost-consuming procedure as integration ratio increases is the testing step. In this paper, we propose a new method, “Efficient TP(test point) assignment algorithm” using “input grouping”, This is helpful method to reducing test length without losing fault coverage. Experimental results show that proposed method reduces test length remarkably and doesn't miss fault coverage, with low hardware overhead Increasing.

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