• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.2
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• pp.328-338
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• 2017

In this paper, a zero torque control scheme adopting current sharing function (CSF) used in integrated Switched Reluctance Motor (SRM) drive with DC battery charger is proposed. The proposed control scheme is able to achieve the keeping position (KP), zero torque (ZT) and power factor correction (PFC) at the same time with a simple novel current sharing function algorithm. The proposed CSF makes the proper reference for each phase windings of SRM to satisfy the total charging current of the battery with zero torque output to hold still position with power factor correction, and the copper loss minimization during of battery charging is also achieved during this process. Based on these, CSFs can be used without any recalculation of the optimal current at every sampling time. In this proposed integrated battery charger system, the cost effective, volume and weight reduction and power enlargement is realized by function multiplexing of the motor winding and asymmetric SR converter. By using the phase winding as large inductors for charging process, and taking the asymmetric SR converter as an interleaved converter with boost mode operation, the EV can be charged effectively and successfully with minimum integral system. In this integral system, there is a position sliding mode controller used to overcome any uncertainty such as mutual inductance or DC offset current sensor. Power factor correction and voltage adaption are obtained with three-phase buck type converter (or current source rectifier) that is cascaded with conventional SRM, one for wide input and output voltage range. The practicability is validated by the simulation and experimental results by using a laboratory 3-hp SRM setup based on TI TMS320F28335 platform.

• The KIPS Transactions:PartC
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• v.14C no.4
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• pp.349-358
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• 2007

Ethernet Passive Optical Network(EPON), which is one of PON technologies for realizing FTTx(Fiber-To-The-Curb/Home/Office), can cost-effectively construct optical access networks. In addition, EPON can provide high transmission rate up to 10Gbps and it is compatible with existing customer devices equipped with Ethernet card. To effectively control frame transmission from ONUs to OLT EPON can use Multi-Point Control Protocol(MPCP) with additional control functions in addition to Media Access Control(MAC) protocol function. For EPON, many researches on intra- and inter-ONU scheduling algorithms have been performed. Among the inter-ONU scheduling algorithms, IPS(Interleaved Polling with Stop) based on polling scheme is efficient because OLT assigns available time portion to each ONU given the request information from all ONUs. Since the IPS needs an idle time period on uplink between two consecutive frame transmission periods, it wastes time without frame transmissions. In this paper, we propose a dynamic bandwidth allocation algorithm to increase the channel utilization on uplink and evaluate its performance using simulations. The simulation results show that the proposed Two-phase Cycle Danamic Bandwidth Allocation(TCDBA) algorithm improves the throughput about 15%, compared with the IPS and Fast Gate Dynamic Bandwidth Allocation(FGDBA). Also, the average transmission time of the proposed algorithm is lower than those of other schemes.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.193-197
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• 2001

This paper presents a novel circuit topology of the double two-switch forward type high frequency transformer linked soft-switching PWM DC-DC power converter with tapped inductor filters that can operate under a condition of the low peak voltage stress across the power semiconductor devices and lowered peak current stress through the transformer for some high power applications. This circuit topology of an interleaved two-switch forward soft-switching power converter is proposed in the order to minimize an idle circulating current due to the tapped inductor filter without of any additional active auxiliary resonant-assisted snubber circuits, such as active resonant DC link snubbers and AC link snubbers, active resonant commutation leg link snubbers. The unique advantages of this power converter are less power circuit components and power semiconductor devices, constant frequency PWM scheme, cost effective configuration and wider soft-switching PWM operation range under PWM power regulations load variations. The practical effectiveness of the proposed soft-switching converter circuit topology is tested by simulations and is proved by experimental results received from the 500W-100kHz breadboard setup.

• Journal of Power Electronics
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• v.10 no.1
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• pp.9-13
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• 2010

This paper proposes an input-series-output-parallel connected ZVS full bridge converter with interleaved control for photovoltaic power conditioning systems (PV PCS). The input-series connection enables a fully modular power-system architecture, where low voltage and standard power modules can be connected in any combination at the input and/or at the output, to realize any given specifications. Further, the input-series connection enables the use of low-voltage MOSFETs that are optimized for a very low RDSON, thus, resulting in lower conduction losses. The system costs decrease due to the reduced current, and the volumes of the output filters due to the interleaving technique. A topology for a photovoltaic (PV) dc/dc converter that can dramatically reduce the power rating and increase the efficiency of a PV system by analyzing the PV module characteristics is proposed. The control scheme, consisting of an output voltage loop, a current loop and input voltage balancing loops, is proposed to achieve input voltage sharing and output current sharing. The total PV system is implemented for a 10-kW PV power conditioning system (PCS). This system has a dc/dc converter with a 3.6-kW power rating. It is only one-third of the total PV PCS power. A 3.6-kW prototype PV dc/dc converter is introduced to experimentally verify the proposed topology. In addition, experimental results show that the proposed topology exhibits good performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.7
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• pp.677-684
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• 2003

This paper addresses the subblock phase weighting(SPW) method to reduce the PAPR in OFDM system. This method divides the input block of OFDM signal into many subblocks and lower the peak power by weighting the phase of each subblocks properly. SPW method can be realized by only one IFFT. PAPR reduction performance is novelly examined when the adjacent, interleaved and random subblock partitioning schemes are used in the SPW system. The random subblock partition scheme has the most effective. More subblocks can effectively reduce the PAPR, but there is a problem that the processing time of iteration is increased. We propose a new weighting factor combination of the complementary sequence characteristic with threshold technique. OFDM data can be recovered by the inserted side information of weighting factor in the feed forward type. Also, BER performance of this SPW system is analyzed when error happens in the side information.

• Investigative Magnetic Resonance Imaging
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• v.21 no.2
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• pp.71-81
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• 2017

Purpose: To compare three, motion-resistant, T1-weighted MR sequences on the hepatobiliary phase for gadoxetic acid-enhanced MR imaging of the liver. Materials and Methods: In this retrospective study, 79 patients underwent gadoxetic acid-enhanced, 3T liver MR imaging. Fifty-nine were examined using a standard protocol, and 20 were examined using a motion-resistant protocol. During the hepatocyte-specific phase, three MR sequences were acquired: 1) gradient recalled echo (GRE) with controlled aliasing in parallel imaging results in higher acceleration (CAIPIRINHA); 2) radial GRE with the interleaved angle-bisection scheme (ILAB); and 3) radial GRE with golden-angle scheme (GA). Two readers independently assessed images with motion artifacts, streaking artifacts, liver-edge sharpness, hepatic vessel clarity, lesion conspicuity, and overall image quality, using a 5-point scale. The images were assessed by measurement of liver signal-to-noise ratio (SNR), and tumor-to-liver contrast-to-noise ratio (CNR). The results were compared, using repeated post-hoc, paired t-tests with Bonferroni correction and the Wilcoxon signed rank test with Bonferroni correction. Results: In the qualitative analysis of cooperative patients, the results for CAIPIRINHA had significantly higher ratings for streak artifacts, liver-edge sharpness, hepatic vessel clarity, and overall image quality as compared to, radial GRE, (P < 0.016). In the imaging of uncooperative patients, higher scores were recorded for ILAB and GA with respect to all of the qualitative assessments, except for streak artifact, compared with CAIPIRINHA (P < 0.016). However, no significant differences were found between ILAB and GA. For quantitative analysis in uncooperative patients, the mean liver SNR and lesion-to-liver CNR with radial GRE were significantly higher than those of CAIPIRINHA (P < 0.016). Conclusion: In uncooperative patients, the use of the radial GRE sequence can improve the image quality compared to GRE imaging with CAIPIRINHA, despite the data acquisition methods used. The GRE imaging with CAIPIRINHA is applicable for patients without breath-holding difficulties.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.