• 한국통신학회논문지
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• 제34권11A호
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• pp.815-821
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• 2009

본 논문에서는 두 명의 상호협력 사용자가 추가적인 대역을 사용하지 않고도 서로의 데이터를 공간적으로 다중화 할 수 있는, 공간적으로 좌표 재배열된 직교 설계 기반의 새로운 상호협력 통신 기법을 제안한다. 제안하는 기법은 기존의 상호협력 통신기법에 비해 다이버시티 이득 (다이버시티 이득 2) 뿐만 아니라 추가적인 코딩 이득을 얻을 수 있음을 보인다. 상호협력 통신에 참여하는 특정 사용자 노드가 자신과 짝을 이루어 동일한 목적지 노드(즉, 셀룰러 네트워크에서의 기지국)와 통신할 수 있는 또 다른 사용자 노드를 찾을 수만 있다면, 제안하는 기법을 통해 셀룰러 네트워크에서 상향링크의 비트 오류율 성능을 향상시킬 수 있음을 시뮬레이션 결과를 통해 확인한다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.195-196
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• 2012

In recent years, in an effort to improve the efficiency and the power density of the front-end power factor correction(PFC), the interleaving of multiple converter is employed. The conventional interleaved continuous conduction mode(CCM) boost PFC converter requires input and output voltage sensing and three current sensing to obtain current balancing between modules. In this paper, the interleaved CCM PFC converter based on modulated carrier control is proposed. With the proposed method, two phase interleaved PFC can be realized simply without line voltage sensing resistor and can achieve current balancing without additional current sensing resistor on common return path. The simulation studies are carried out to verify the effectiveness of the proposed control scheme.

• 대한전자공학회논문지TC
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• 제46권1호
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• pp.32-39
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• 2009

송신 단에서 채널 상태 정보를 알고 있는 폐루프 시스템은 개방 루프 시스템에 비하여 더 효율적인 전송을 수행할 수 있다. 그러나 실제 시스템은 제한된 피드백 채널을 가지므로 송신단에서 완벽한 채널 정보를 알 수 없으며, 따라서 부분 채널 정보를 활용하는 시스템의 설계가 중요한 요소로 부각되고 있다. 특히, 모바일 환경에서는 사용자의 이동성으로 인하여 채널 상태가 유동적으로 변화하며 이는 성능의 열화를 초래한다. 본 논문에서는 비트 인터리버와 결합한 부호화된 직교 주파수 다중 분할(BIC-OFDM; Bit-Interleaved Coded Orthogonal Frequency Division Multiplexing) 시스템을 위하여 채널 변화에 적절히 대응하는 적응 변조 코딩 기법을 제안한다. 합리적인 피드백 정보량을 통해, 제안하는 기법은 도플러 확산에 의한 채널 변화를 보상하여 향상된 성능을 제공한다. 실험 결과를 통해 제안하는 기법이 정확한 비트 에러율의 추정을 통한 성능 이득을 가짐을 확인한다.

• Journal of Electrical Engineering and Technology
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• 제12권3호
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• pp.1156-1165
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• 2017

A high performance interleaved bridgeless boost power factor correction (PFC) rectifier operating under the critical current conduction mode (CrM) is proposed in this paper to improve the efficiency and system performance of various applications, such as nano-grid systems. By combining the interleaved technique with the bridgeless topology, the circuit contains two independent branches without rectifier diodes. The branches operate in interleaved mode for each respective half-line period. Moreover, when operating in CrM, all the power switches take on soft-switching, thereby reducing switching losses and raising system efficiency. In addition, the input current flows through a minimum amount of power devices. By employing a commercial PFC controller, an effective control scheme is used for the proposed circuit. The operating principle of the proposed circuit is presented, and the design considerations are also demonstrated. Simulations and experiments have been carried out to evaluate theoretical analysis and feasibility of the proposed circuit.

• Journal of Power Electronics
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• 제10권2호
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• pp.132-137
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• 2010

Interleaving techniques are widely used to reduce input/output ripples and to increase the power capacity of boost converters operating in critical conduction mode. Two types of phase-shift control schemes are studied in this paper, the turn-on time shifting method and the turn-off time shifting method. It is found that although the turn-off time shifting method exhibits better performance, it suffers from sub-harmonic oscillations at high input voltages. To solve this problem, an intensive quantitative analysis of the sub-harmonic oscillation phenomenon is made in this paper. Based upon that, a novel modified turn off time shifting control scheme for interleaved boost converters operating in critical conduction mode is proposed. An important advantage of this scheme is that both the master phase and the slave phase can operate stably in critical conduction mode without any oscillations in the full input voltage range. This method is implemented with a FPGA based digital PWM control platform, and tests were carried out on a two-phase interleaved boost PFC converter prototype. Experimental results demonstrated the feasibility and performance of the proposed phase-shift control scheme.

• Journal of international Conference on Electrical Machines and Systems
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• 제3권1호
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• pp.88-92
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• 2014

This paper presents an application of a multiphase interleaved converter in tracking maximum power points (MPPs) of a photovoltaic (PV) panel regardless of environmental variations. Maximum power from the panel was extracted by means of the well-known the perturb-and-observe (P&O) method. The switching control technique used an interleaving scheme based on multi-unit synchronization. The converter performed harmonic attenuation without affecting the tracking speed. This approach is straightforward, reliable and inexpensive, and could be applied to any higher number of switching cells without difficulty.

• Journal of international Conference on Electrical Machines and Systems
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• 제1권1호
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• pp.99-103
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• 2012

This paper presents a new switch-control approach for multiphase interleaved converters. Development of the proposed technique is based on control-signal generation for multi-unit synchronization. Current sharing among the switching cells and voltage regulation are achieved by means of a multi-loop control scheme regardless of changes in input voltage and load. System stability is ensured by single-pole compensation. This proposed technique is straightforward, reliable and inexpensive, and can be applied to any higher number of cells without difficulty.

• Journal of Electrical Engineering and Technology
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• 제9권5호
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• pp.1632-1642
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• 2014

This paper presents an interleaved resonant converter to reduce the voltage stress of power MOSFETs and achieve high circuit efficiency. Two half-bridge converters are connected in series at high voltage side to limit MOSFETs at $V_{in}/2$ voltage stress. Flying capacitor is used between two series half-bridge converters to balance two input capacitor voltages in each switching cycle. Variable switching frequency scheme is used to control the output voltage. The resonant circuit is operated at the inductive load. Thus, the input current of the resonant circuit is lagging to the fundamental input voltage. Power MOSFETs can be turn on under zero voltage switching. Two resonant circuits are connected in parallel to reduce the current stress of transformer windings and rectifier diodes at low voltage side. Interleaved pulse-width modulation is adopted to decrease the output ripple current. Finally, experiments are presented to demonstrate the performance of the proposed converter.

• Journal of applied mathematics & informatics
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• 제16권1_2호
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• pp.469-481
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• 2004

In this paper, we investigate the mean queue length and the mean packet delay of a dynamic bandwidth allocation(DBA) scheme in an Ethernet passive optical network(EPON). We focus on the interleaved polling system with a gated service discipline. We assume that input packets arrive at an optical network unit(ONU) according to Poisson process. We use a continuous time queueing model in order to find the queue length distribution of the gated interleaved polling system with the first stage input queue and the second stage transmission queue. We give some numerical results to investigate the mean queue lengths and mean packet delays for the symmetric polling system with statistically identical stations.

• 전력전자학회논문지
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• 제27권5호
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• pp.417-424
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• 2022

This study proposes a current-balancing technique for an interleaved buck converter using a variable inductor and a snubber capacitor. The proposed scheme balances the inductor current by using the variable inductor and enables zero voltage switching under all load ranges. With the variable inductor, the ripple of inductor current changes according to load variation. In addition, a 1.6 kW prototype is built to verify the validity of the proposed scheme, and the experimental results are successfully obtained.