• 제목/요약/키워드: Interleaved Mode

검색결과 106건 처리시간 0.019초

DESIGN CONCEPT FOR SINGLE CHIP MOSAIC CCD CONTROLLER

  • HAN WONYONG;JIN Ho;WALKER DAVID D.;CLAYTON MARTIN
    • 천문학회지
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    • 제29권spc1호
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    • pp.389-390
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    • 1996
  • The CCDs are widely used in astronomical observations either in direct imaging use or spectroscopic mode. However, the areas of available sensors are too small for large imaging format. One possibility to obtain large detection area is to assemble mosaics of CCD, and drive them simultaneously. Parallel driving of many CCDs together rules out the possibility of individual tuning; however, such optimisation is very important, when the ultimate low light level performance is required, particularly for new, or mixed devices. In this work, a new concept is explored for an entirely novel approach, where the drive waveforms are multiplexed and interleaved. This simultaneously reduces the number of leadout connections and permits individual optimisation efficiently. The digital controller can be designed within a single EPLD (Erasable Programmable Logic Device) chip produced by a CAD software package, where most of the digital controller circuits are integrated. This method can minimise the component. count., and improve the system efficiency greatly, based on earlier works by Han et a1. (1996, 1994). The system software has an open architecture to permit convenient modification by the user, to fit their specific purposes. Some variable system control parameters can be selected by a user with a wider range of choice. The digital controller design concept allows great flexibility of system parameters by the software, specifically for the compatibility to deal with any number of mixed CCDs, and in any format, within the practical limit.

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Medium Voltage Resonant Converter with Balanced Input Capacitor Voltages and Output Diode Currents

  • Lin, Bor-Ren;Du, Yan-Kang
    • Journal of Power Electronics
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    • 제15권2호
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    • pp.389-398
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    • 2015
  • This paper presents a 1.92 kW resonant converter for medium voltage applications that uses low voltage stress MOSFETs (500V) to achieve zero voltage switching (ZVS) turn-on. In the proposed converter, four MOSFETs are connected in series to limit the voltage stress of the power switches at half of the input voltage. In addition, three resonant circuits are adopted to share the load current and to reduce the current stress of the passive components. Furthermore, the transformer primary and secondary windings are connected in series to balance the output diode currents for medium power applications. Split capacitors are adopted in each resonant circuit to reduce the current stress of the resonant capacitors. Two balance capacitors are also used to automatically balance the input capacitor voltage in every switching cycle. Based on the circuit characteristics of the resonant converter, the MOSFETs are turned on under ZVS. If the switching frequency is less than the series resonant frequency, the rectifier diodes can be turned off under zero current switching (ZCS). Experimental results from a prototype with a 750-800 V input and a 48V/40A output are provided to verify the theoretical analysis and the effectiveness of the proposed converter.

개선된 DC-DC 양방향 컨버터 (Improved DC-DC Bidirectional Converter)

  • 김성환;허재정;정범동;윤경국
    • Journal of Advanced Marine Engineering and Technology
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    • 제41권1호
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    • pp.76-82
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    • 2017
  • 최근 전자제어엔진 및 전기추진선박이 도입된 이래, 배터리를 사용하는 비상 전력공급시스템에서 무정전 전원공급장치의 중요성이 강조되어왔다. 비상 전력공급시스템에서 양방향 컨버터는 중요한 구성요소이다. 본 연구에서는 개선된 DC-DC 양방향 컨버터의 토폴로지를 제시한다. 이것은 기존의 컨버터에 비해 전압변환율은 증가되고 스위치에 인가되는 전압 스트레스는 감소되는 장점을 지닌다. 제안된 컨버터의 성능을 확인하기 위해 소프트웨어 PSIM을 사용하여 시뮬레이션을 수행하였다. 이 컨버터의 변환율은 기존의 컨버터에 비해 승압모드에서 4배, 강압모드에서 1/4배 이었고 스위치에 걸리는 전압은 고압 측의 1/4배 이었다. 또한 블로킹 커패시터가 전하를 균등하게 분배하기 때문에 다른 추가 제어회로 없이 인터리브 모듈 사이에서 전하가 균등하게 분담된다는 것을 확인하였다.

디지털 제어 기반의 경계점모드 브릿지리스 PFC 컨버터 (Critical Conduction Mode Bridgeless PFC Converter Based on a Digital Control)

  • 김태훈;이우철
    • 전기학회논문지
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    • 제65권12호
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    • pp.2000-2007
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    • 2016
  • Generally, in order to implement the CRM(Critical Conduction Mode), the analog controller is used rather than a digital controller because the control is simple and uses less power. However, according to the semiconductor technology development and various user needs, digital control system based on a DSP is on the rise. Therefore, in this paper, the CRM bridgeless PFC converter based on a digital control is proposed. It is necessary to detect the inductor current when it reaches zero and peak value, for calculating the on time and off time by using the current information. However, in this paper, the on-time and off-time are calculated by using the proposed algorithm without any current information. If the switching-times are calculated through the steady-state analysis of the converter, they do not reflect transient status such as starting-up. Therefore, the calculated frequency is out of range, and the transient current is generated. In order to solve these problems, limitation method of the on-time and off-time is used, and the limitation values are varied according to the voltage reference. In addition, in steady state, depending on the switching frequency, the inductance is varied because of the resonance between the inductor and the parasitic capacitance of the switching elements. In order to solve the problem, inductance are measured depending on the switching frequency. The measured inductance are used to calculate the switching time for preventing the transient current. Simulation and experimental results are presented to verify the proposed method.

충전기 겸용 스위치드 릴럭턴스 전동기의 제로토크제어 (Zero Torque Control of Switched Reluctance Motor for Integral Charging)

  • 라쉬디;나마찌;세헤이안;이동희;안진우
    • 전기학회논문지
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    • 제66권2호
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    • pp.328-338
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    • 2017
  • In this paper, a zero torque control scheme adopting current sharing function (CSF) used in integrated Switched Reluctance Motor (SRM) drive with DC battery charger is proposed. The proposed control scheme is able to achieve the keeping position (KP), zero torque (ZT) and power factor correction (PFC) at the same time with a simple novel current sharing function algorithm. The proposed CSF makes the proper reference for each phase windings of SRM to satisfy the total charging current of the battery with zero torque output to hold still position with power factor correction, and the copper loss minimization during of battery charging is also achieved during this process. Based on these, CSFs can be used without any recalculation of the optimal current at every sampling time. In this proposed integrated battery charger system, the cost effective, volume and weight reduction and power enlargement is realized by function multiplexing of the motor winding and asymmetric SR converter. By using the phase winding as large inductors for charging process, and taking the asymmetric SR converter as an interleaved converter with boost mode operation, the EV can be charged effectively and successfully with minimum integral system. In this integral system, there is a position sliding mode controller used to overcome any uncertainty such as mutual inductance or DC offset current sensor. Power factor correction and voltage adaption are obtained with three-phase buck type converter (or current source rectifier) that is cascaded with conventional SRM, one for wide input and output voltage range. The practicability is validated by the simulation and experimental results by using a laboratory 3-hp SRM setup based on TI TMS320F28335 platform.

EPON에서 하향 데이터 전송을 고려한 동적 대역폭 할당 방안 (Dynamic Bandwidth Allocation Scheme with Considering Downstream Traffic in EPON)

  • 김은철;이강원;최영수;조유제
    • 대한전자공학회논문지TC
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    • 제42권12호
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    • pp.37-44
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    • 2005
  • EPON 환경에서 효율적인 상향 채널의 사용을 위해 다양한 동적 대역폭 할당 방안이 제안되고 있다. 일반적으로 가변 폴링 주기 방안은 고정 폴링 주기 방안에 비해 optical network unit(ONU)의 대역폭 요청량을 보다 유연하게 반영하여 폴링 주기를 결정하기 때문에 상향 채널에서 향상된 전송 성능을 나타낸다. 그러나, 가변 폴링 주기 방안은 ONU의 상향 트래픽 부하가 낮은 환경에서는 폴링 오버헤드에 의한 하향 채널의 대역폭 낭비가 심한 문제점이 있다. 본 논문에서는 Ethernet passive optical network(EPON)에서 가변 폴링 주기와 고정 폴링 주기 방안의 장점만을 취한 새로운 동적 대역폭 할당 방안을 제안한다. 제안한 방안은 대표적인 가변 폴링 주기 방안인 interleaved polling with adaptive cycle time(IPACT) 방안에 기반을 두고, 하향전송을 위한 optical line terminal(OLT) 큐의 상태에 따라 가변 폴링 주기 혹은 고정 폴링 주기로 동작한다. 시뮬레이션을 통해 제안 방안은 상향 전송에서 IPACT 방안과 유사한 지연 성능을 유지하면서도 하향 전송에서는 고정 폴링 주기 방안에 근접하는 수율을 나타냄을 보였다.