• Journal of Sensor Science and Technology
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• v.5 no.6
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• pp.60-67
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• 1996

The interfacial electrical properties of InSb MIS structure with low temperature remote PECVD $SiO_{2}$ have been characterized. The interlace-state density at mid-bandgap of the MIS structure was about $1{\sim}2{\times}10^{11}\;cm^{-2}eV^{-1}$, when the $SiO_{2}$ film was deposited at $105^{\circ}C$. However, large amount of interlace states and trap states were observed in the MIS structure fabricated at temperatures above $105^{\circ}C$. The time constant of $10^{-4}{\sim}10^{-5}\;sec$ of interface states was extracted from G- V measurement. As the deposition temperature increased, the hysteresis of C- V curves were increased due to the high trap density.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.6
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• pp.304-310
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• 2002

Novel charge trap type memory devices with reoxidized oxynitride gate dielectrics made by NO annealing and reoxidation process of initial oxide on substrate have been fabricated using 0.35 $\mu \textrm{m}$ retrograde twin well CMOS process. The feasibility for application as NVSM memory device and characteristics of traps have been investigated. For the fabrication of gate dielectric, initial oxide layer was grown by wet oxidation at $800^{\circ}C$ and it was reoxidized by wet oxidation at $800^{\circ}C$ after NO annealing to form the nitride layer for charge trap region for 30 minutes at $850^{\circ}C$. The programming conditions are possible in 11 V, 500 $\mu \textrm{s}$ for program and -13 V, 1ms for erase operation. The maximum memory window is 2.28 V. The retention is over 20 years in program state and about 28 hours in erase state, and the endurance is over $3 \times 10^3$P/E cycles. The lateral distributions of interface trap density and memory trap density have been determined by the single junction charge pumping technique. The maximum interface trap density and memory trap density are $4.5 \times 10^{10} \textrm{cm}^2$ and $3.7\times 10^{18}/\textrm{cm}^3$ respectively. After $10^3$ P/E cycles, interlace trap density increases to $2.3\times 10^{12} \textrm{cm}^2$ but memory charges decreases.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.4
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• pp.350-354
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• 2009

$Al_{2}O_{3}$ thin films were deposited on GaN(0001) by using a Remote Plasma Atomic Layer Deposition(RPALD) technique with a trimethylaluminum(TMA) precursor and oxygen radicals in the temperature range of $25{\sim}500^{\circ}C$. The growth rate per cycle was varied with the substrate temperature from $1.8{\AA}$/cycle at $25^{\circ}C$ to $0.8{\AA}$/cycle at $500^{\circ}C$. The chemical structure of the $Al_{2}O_{3}$ thin films was studied using X-ray photoelectron spectroscopy(XPS). The electrical properties of $Al_{2}O_{3}$/GaN Metal-Insulator-Semiconductor (MIS) capacitor grown at a $300^{\circ}C$ process temperature were excellent, a low electrical leakage current density(${\sim}10^{-10}A/cm^2$ at 1 MV) at room temperature and a high dielectric constant of about 7.2 with a thinner oxide thickness of 12 nm. The interface trap density($D_{it}$) was estimated using a high-frequency C-V method measured at $300^{\circ}C$. These results show that the RPALD technique is an excellent choice for depositing high-quality $Al_{2}O_{3}$ as a Sate dielectric in GaN-based devices.