• Journal of the Korean Institute of Telematics and Electronics A
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• 제32A권7호
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• pp.115-122
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• 1995

This paper presents the simulation environment that verifies whether a new microprocessor described with HDL is compatible with MS-DOS. The phrase 'compatible with MS-DOS' means that the microprocessor can execute MS-DOS without any modification of MS-DOS's binary code. The proposed verification environment consists of HDL simulator and user interface module. And the communications between them are performed by using sockets which UNIXprovide. The HDL simulator is equipped with several functions, which use PLI to emulate ROM-BIOS facilities. The ROM-BIOS emulation routine is described by using these functions. User interface module utilizes S/MOTIF and participates in emulating PC monitor and keyboard. The verification environment is tested by executing the MS-DOS commands (DIR, FORMAT, DATE, TIME etc.) with the HDL model of microprocessor, and the display of user interface module verifies that the environment works correctly. In this paper, the method of constructing the verification environment is presented, and the simulation results are summarized.

• Journal of Platform Technology
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• 제10권4호
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• pp.25-38
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• 2022

Recently, it is reported that the Korean Unmanned Aerial Vehicle (UAV) interface protocol (K-4586) based on STANAG-4586 is being developed to secure interoperability between UAVs. The core elements of the K-4586-based Unmanned Aircraft System (UAS) are the Core UAV Control System (CUCS), Vehicle Specific Module (VSM), Data Link Interface (DLI), and C4I systems. In UAS based on K-4586, the DLI function for transmitting and receiving messages to link UAVs is included in VSM and CUCS respectively. The Generator/Analyzer (G/A) tool is an apparatus that is developed for protocol conformance verification for VSM and CUCS, and G/A tools with DLI message transmitting and receiving should be developed separately. Core applications (VSM, CUCS, DLI) and G/A tools based on K-4586 may be developed independently depending on the developers. If the DLI message modules are different for each developer, the scope and results of protocol conformance verification will be dissimilar, and some problems may happen during system integration. In this study, common DLI message module based on the API was designed to provide the DLI message transmitting and receiving function necessary to the development of core applications and the protocol conformance verification tool of based on K-4586. When applying the proposed common DLI message module, it can be expected to shorten the UAS system development period and reduce costs, and ensure conformance of protocol. In this paper, the design and implementation method for the common DLI message module based on API was proposed and the results of functional test was described.

• The Transactions of The Korean Institute of Electrical Engineers
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• 제63권12호
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• pp.1747-1751
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• 2014

Interlocking system along with point machine for efficient route control secures safety of train operation by interchanging information each other. However, various types of interlocking system and point machine operating on bender specific interface bring obstacles to effective maintenance and safety. In this paper, we have investigated on interface methods to suggest standard interface module applicable to various operating system

• Proceedings of the KIEE Conference
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.388-390
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• 2006

This paper presents a hybrid SoC design for phase detection of single tone signal. The designed hybrid SoC is composed of three functional blocks, i.e., an analog to digital converter module, a phase detection module and a controller module. A design of the controller module is based on a 16-bit RISC architecture. An I/O interface and an LCD control interface for transmission and display of phase measurement values are included in the design of the controller module. A design of the phase detector is based on a recursive sliding-DFT. The recursive architecture effectively reduces the gate numbers required in the implementation of the module. The ADC module includes a single-bit second-order sigma-delta modulator and a digital decimation filter. The decimation filter is designed to give 98dB of SNR for the ADC. The effective resolution of the ADC is enhanced to 98dB of SNR by the incorporation of a pre FIR filter, a 2-stage cascaded integrator- comb(CIC) filter and a 30-tab FIR filter in the decimation. The hybrid SoC is verified in FPGA and implemented in 0.35 CMOS Technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제11권8호
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• pp.1478-1485
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• 2007

In this paper, a meteorological system including a wind speed & direction module and the DSP(Digital Signal Processor) sensor interface circuit board are proposed. This DSP system accepts and process the informations from a wind speed & direction module, the atmospheric pressure sensor, the ambient air temperature sensor and transfers it to the PC monitoring system. Especially, a wind speed & direction module and a DSP hardware are directly designed and applied. A wind speed & direction module have a construction that it have four film type RID(Resistive Temperature Detectors) resistive sensor adhered around the circular metal body heated constantly by heating coil for obtaining vector informations about wind. By this structure, the module is enabled precise measurement having a robustness about vibration, humidity, corrosion. A sensor signal processing circuit is using TMS320F2812 TI(Texas Instrument) Corporation high speed DSP. An economical meteorological system could be constructed through the data from wind speed & direction module and by the fast processing of DSP interface circuit board.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제19권5호
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• pp.1125-1130
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• 2015

In this paper, a method to identify components per unit task system is expressed with node, module, and interface. We define security subject per unit task system and explain node, module, and interface per component. According to the defined security standard in design phase, we also perform to design and elaborate security attributes for node and module as identified security subjects in their defined tables. And then we describe the composition standard for security attribute design with some examples, after classifying it into security subject, access subject, access control area, identification or verification area, and encryption.

• Journal of Advanced Navigation Technology
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• 제14권4호
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• pp.545-552
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• 2010

In this paper, we study on a radio multiple sensing interface module to accurately decide serious error sources that are happened by unexpectable problems in industrial fields, in addition, we study a reliability improvement scheme to guarantee the integrity of multiple sensing data. For multiple sensing interface module, communication drivers such as USART, TWI, ADC and GPIO-I2C are implemented. to improve the transmission reliability, reed-Solomon code is used. From the simulation result of this system in indoor environment, we confirm that the reliability of RS coded data is improved about 5 times than uncoded data. Moreover, we prove that multiple sensing interface module is suitable to diagnose error sources of industrial automaton equipment.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 한국조명전기설비학회 2005년도 춘계학술대회논문집
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• pp.283-287
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• 2005

In this paper, one general approach is proposed for the design of power system that can be applicable for next generation LEO satellite application. The power system consists of solar panels, battery, and power control and distribution unit(PCDU). The PCDU contains solar array modules, battery interface modules, low-voltage power distribution modules, high-voltage distribution modules, heater power distribution modules, on-board computer interface modules, and internal DC/DC converter modules. The PCDU plays roles of protection of battery against overcharge by active control of solar array generated power, distribution of unregulated electrical power via controlled outlets to bus and instrument units, distribution of regulated electrical power to selected bus and instrument units, and provision of status monitoring and telecommand interface allowing the system and ground operate the power system, evaluate its performance and initiate appropriate countermeasures in case of abnormal conditions. We review the functional schemes of the main constitutes of the PCDU such as the battery interface module, the auxiliary supply module, solar array regulators with maximum power point tracking(MPPT) technology, heater power distribution modules, spacecraft unit power distribution modules, and instrument power distribution module.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.1159-1162
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• 2003

Recently we suffered lot of failures of polymer surge arresters made by same manufacture after one year field operation. In order to set up countermeasures we investigated the causes of failures. We extracted faulted arresters and sound ones which were installed in same pole with faulted ones for the electrical test and dissection. 44 arresters were removed from 8 branch offices. Almost all of faulted arresters hadtracking damage on the interface between inner module and housing and the surface of inner module was very rough and irregular. It was possible to occur moisture ingress into the interface between inner module and housing due to the void of the interface and non tight sealing caps. Lots of sound arresters were failed during the moisture ingress test. This result must relate with tracking damage of faulted arresters. Therefore we can say that arresters had poor interface and sealing system. But we could not found aging and defects of ZnO elements because the electrical performance except moisture ingress test of arresters showed good.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제40권5호
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.