• Journal of the Korean Society for Precision Engineering
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• v.13 no.5
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• pp.104-114
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• 1996

For the improvement of productivity, the reduction of cost and time for manufacturing is mandatory, especially in the field of electromic industry. The study is concerned with a practical means of systematic assistance to formability estimation and selection of reliable design specification for electronic sheet metal parts. The objective of this research work is to develop a simulation system which hops to analyze the target processes with the finite element method and to acquire available design data quickly and exactly. The simulation system developed in the study consists of design verification, selection of optimal combination of parameters, knowledge acquisition and graphical user interface(GUI). Design verification is automatically carried out by using the finite element method. A data base management system and nomograms are utilized for knowledge acquisition. The developed system has been applied to some major sheet metal forming operations such as flanging, embossing, bending and blanking. According to the simulated results, the validation of the target processes has been confirmend. Analysis data, estimation rules of formability and graphical representation of the analysis have been employed for the designer's understanding and evaluation, thus providing a practical means of robust design and evaluation of forma- bility for producing electronic sheet metal parts.

• Proceedings of the Korea Water Resources Association Conference
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• 2004.05b
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• pp.1400-1403
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• 2004

The current industrial development and the Increase of population along Nakdong River have produced a rapid Increase of wastewater discharge. This has resulted in problem of water quality control and management. Although many efforts have been carried out, water quality has not significantly improved. The goal of this study is to design a NGIS-based water quality management system for the scientific water quality control and management in the Nakdong River. For general water quality analysis, QULA2E model was applied to the Nakdong River. A sensitivity analysis was made to determine significant parameters and an optimization was made to estimate optimal values. The calibration and verification were performed by using observed water quality data for Nakdong River. A water qualify management system for Nakdong River was made by connecting the QUAL2E model to ArcView. It allows a Windows-based Graphic User Interface(GUI) to implement all operation with regard to water quality analysis. The modeling system in this study will be an efficient NGIS for planning of water quality management.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.6
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• pp.380-387
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• 2004

In accordance with the computerization of railway signaling systems, the interface link between the signaling systems has been replaced by a digital communication channel. At the same time, the importance of the communication link has become increasingly significant. However, there are some questionable matters in the current state of railway signaling systems in KNR. First, different communication protocols have been applied to create an interface between railway signaling systems although the protocols have the same functions. Next, the communication protocols currently used in the railway fields have some illogical parts such as structure, byte formation, error correction scheme, and so on. To solve these matters, the standard communication protocol for railway signaling systems is designed. The newly designed protocol is overviews in this paper. And the simulation is performed to analysis the performance of data link control for designed protocol. According to this simulation, it is identified that the link throughput of new protocol is improved about 10% and the frame error rate is improved than existing protocol. And it is verified the safety and liveness properties of designed protocol by using a formal method for specifying the designed protocol. It is expected that there will be an increase in safety, reliability and efficiency in terms of the maintenance of the signaling systems by using the designed communication protocol for railway signaling.

• Journal of IKEEE
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• v.26 no.3
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• pp.437-444
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• 2022

This paper proposes a CRC error verification method for SPI and I2C buses of automotive semiconductors. In automotive semiconductors, when an error occurs in communication and an incorrect value is transmitted, fatal results may occur. Unlike LIN communication and CAN communication, in communication such as SPI and I2C, there is no frame for detecting an error, so some definitions of new standards are required. Therefore, in this paper, the CRC error detection mode is newly defined in the SPI and I2C communication protocols, and the verification is presented by designing it in hardware.

• Journal of Internet Computing and Services
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• v.3 no.5
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• pp.9-17
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• 2002

CSIX-L1 is the Common Switch Interface that defines a physical interface for transferring information between a traffic manager (Network Processor) and a switching fabric in ATM, IP, MPLS, Ethernet and data communication areas. In Tx, data to be transmitted is generated in Cframe which is the base information unit and in Rx, original data is extracted from the received Cframe. CSIX-L1 suppots the 32, 64, 96, and 123-bit interface and generates a variable length CFrame and Idle Cframe. Also CSIX-L1 appends Padding byte and supports 16-bit Vertical parity, CSIX-L1 is designed using Xilinx 4,1i. After functional and timing simulations are completed. CSIX-L1 module is downloaded in Xilinx FPGA XCV1000EHQ240C and verified. The synthesized CSIX module operates at 27MHz.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.309-314
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• 2011

As a system becomes more complex, a design relies more heavily on a methodology based on high-level abstraction and functional verification. SystemVerilog includes characteristics of hardware design language and verification language in the form of extensions to the Verilog HDL. However, the OOP of System Veri log does not allow multiple inheritance. In this paper, we propose adoption of SystemC to introduce multiple inheritance. After being created, a SystemC unit is combined with a SystemVerilog-based verification environment using SystemVerilog DPI and ModelSim macro. Employing multiple inheritance of SystemC makes a design of a verification environment simple and easy through source code reuse. Moreover, a verification environment including SysemC unit has a benefit of reconfigurability due to OOP.

• Journal of the Korea Society of Computer and Information
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• v.27 no.12
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• pp.209-217
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• 2022

Naval CMS(Combat Management System) is linked to various sensors and weapon equipment and use DDS(Data Distribution Service) for efficient data communication between ICU(Interface Control Unit) Node and IPN(Information Processing Node). In order to use DDS, software in the system communicates in an PUB/SUB(Publication/Subscribe) based on DDS topic. If the DDS messages structure in this PUB/SUB method does not match, problems such as incorrect command processing and wrong information delivery occur in sending and receiving application software. To improve this, this paper proposes a DDS message structure integrity verification method. To improve this, this paper proposes a DDS message structure integrity verification method using a hash tree. To verify the applicability of the proposed method to Naval CMS, the message integrity verification rate of the proposed method was measured, and the integrity verification method was applied to CMS and the initialization time of the existing combat management system was compared and the hash tree generation time of the message structures was measured to understand the effect on the operation and development process of CMS. Through this test, It was confirmed that the message structure verification method for system stability proposed in this paper can be applied to the Naval CMS.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1465-1469
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• 2003

In general satellite verification process, the AOCS (Attitude & Orbit Control Subsystem) should be verified through several kinds of verification test which can be divided into two major category like FBT (Fixed Bed Test) and polarity test. And each test performed in different levels such as ETB (Electrical Test Bed) and satellite level. The test method of FBT is to simulate satellite dynamics with sensors and actuators supported by necessary environmental models in ETB level. The VDS (Vehicle Dynamic Simulator) try to make the real situation as possible as the on-board processor will undergo after launch. The purpose of FBT test is to verify that attitude control logic function and hardware interface is designed as expected with closed loop simulation. The VDS is one of major equipments for performing FBT and consists of software and hardware parts. The VDS operates in VME environments with target board, several commercial boards and custom boards based on the VxWorks real time operating system. In order to make time synchronization between VDS and satellite on-board processor, high reliable semaphore was implemented to make synchronization with the interrupt signal from on-board processor. In this paper, the real-time operating environment used on VDS equipment is introduced, and the hardware and software configurations of VDS summarized in the systematic point of view. Also, we try to figure out the operational concept of VDS and AOCS verification test method with close-loop simulation.

• Aerospace Engineering and Technology
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• v.5 no.2
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• pp.108-113
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• 2006

This paper includes the test results of KOMPSAT-2 payload downlink system which were measured for the purpose of performance verification. The antenna beam patterns which indicates the status of the interface & antenna itself, were measured as well as the antenna VSWR. The checkout of the transponder & its spectrum was followed and this made sure that there was no spurious output distinguished. Finally a test for BER verification was conducted between satellite and receiving system for their compatibility through the antenna-to-antenna connection using an antenna hat. Verification tests for an RF system should be performed after relocation, integration and test for environments in order to make sure that no degradation happens.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.40 no.6
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• pp.548-554
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• 2012

Verification and validation of operational software of the flight control computer, which is flight safety critical, is very important to prove correctness and faultness of the software. To verify the real-time softare requirement on operational software of flight control computer, real-time software internal parameter and variable monitoring technics on hardware-in-the-loop environment, similar to on-flight environment, is required. This paper describes flight safety critical software validation and verificiation environment using standard debugging interface, NEXUS 5001.