• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.37 no.7
• /
• pp.701-708
• /
• 2009

The flight control law of developed flight control computer(DFLCC) is developed based on operation flight program of advanced trainer aircraft full scale development final configuration. The flight control law design is used common use development tool in GUI(Graphic User Interface) environment. The flight control law transformed to C-Code is reflected in OFP. The OFP is verified by the standardized verification process. But, before standardized verification process, we need preliminary verification process such as similarity of flight control law and reliability of developed HILS. Similarity of flight control law is verified by comparing the aircraft response of advanced trainer aircraft and those of the developed control law. Also, reliability of developed HILS is verified by comparing the aircraft response of HILS and Non-real time simulation result. This paper verifies similarity of developed control law and reliability of HILS environment as comparing aircraft response.

• Journal of Advanced Research in Ocean Engineering
• /
• v.1 no.1
• /
• pp.36-43
• /
• 2015

Since the crack generation and its propagation caused by welding defects is one of the main hull damage patterns, the simulation of crack propagation process has an important significance for ship safety. Based on interface element method, a finite element model to simulate crack propagation is studied in the paper. A Lennard-Jones type potential function is employed to define potential energy of the interface element. Tensile tests of steel flat plates with initial central crack are carried out. Surface energy density and spring critical stress that are suitable for the simulation of crack propagation are determined by comparing numerical calculation and tests results. Based on a large number of simulation results, the curve of simulation correction parameter plotted against the crack length is calculated.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.22 no.49
• /
• pp.153-161
• /
• 1999

GUI(Graphic User Interface) have an influence on end-user environments in information system. Consistency is one of the most important GUI characteristics. Consistency should apply across the different media which form the total user interface. User can get a lot of benefits through consistency. To achieve consistency of the total interface, the interface standards are very important. The goals of this study is to suggest GUI's development guidelines through analysis of real fields using ERP package in a electric assembly line. The guidelines fall into four functions: inquiry, registration, modification, deletion. The guidelines can be used for better system development later and as verification tool in GUI development.

• Journal of Platform Technology
• /
• v.10 no.4
• /
• pp.25-38
• /
• 2022

Recently, it is reported that the Korean Unmanned Aerial Vehicle (UAV) interface protocol (K-4586) based on STANAG-4586 is being developed to secure interoperability between UAVs. The core elements of the K-4586-based Unmanned Aircraft System (UAS) are the Core UAV Control System (CUCS), Vehicle Specific Module (VSM), Data Link Interface (DLI), and C4I systems. In UAS based on K-4586, the DLI function for transmitting and receiving messages to link UAVs is included in VSM and CUCS respectively. The Generator/Analyzer (G/A) tool is an apparatus that is developed for protocol conformance verification for VSM and CUCS, and G/A tools with DLI message transmitting and receiving should be developed separately. Core applications (VSM, CUCS, DLI) and G/A tools based on K-4586 may be developed independently depending on the developers. If the DLI message modules are different for each developer, the scope and results of protocol conformance verification will be dissimilar, and some problems may happen during system integration. In this study, common DLI message module based on the API was designed to provide the DLI message transmitting and receiving function necessary to the development of core applications and the protocol conformance verification tool of based on K-4586. When applying the proposed common DLI message module, it can be expected to shorten the UAS system development period and reduce costs, and ensure conformance of protocol. In this paper, the design and implementation method for the common DLI message module based on API was proposed and the results of functional test was described.

• Journal of KIISE:Information Networking
• /
• v.29 no.5
• /
• pp.510-523
• /
• 2002

The routers in an active network perform customized computations on the messages flowing through them, while the role of routers in the traditional packet network, such as the Internet, is to passively forward packets as fast as possible. In contrast to the Internet, the processing in active networks can be customized on a per user or per application basis. Active networks allow users to inject information into the network, where the information describes or controls a program to be executed for the users by the routers as well as the end hosts. So the network users can realize the active networks by "programming" the network behavior via the programming interface exposed to them. In this paper, we devise a network protocol model and present a verification technique for reasoning about the correctness of an active application defined using the model. The technique is developed in a platform- and language-independent way, and it is algorithmic and can be automated by computer program. We give an example dealing with network auction to illustrate the use of the model and the verification technique.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.499-502
• /
• 1999

This paper presents a PCI (Peripheral Component Interconnect) controller embedded in a multimedia processor, called FLOVA (FLOating point VLIW Architecture), targeting for 3D graphics applications. Fast I/O interfaces are essential for multimedia processors which usually handle large amount of multimedia data. Therefore, in FLOVA, PCI bus is adopted for I/O interface due to fast burst transaction. However, there are several problems in implementation and verification to use burst transaction of PCI. It is difficult to handle data transaction between two units which have two different operating frequency. FLOVA has more higher operating frequency about 100MHz than that of PCI local bus and it makes lower utilization of FLOVA bus. Also, traditional simulation is not sufficient for verification of PCI functionality. In this paper, we propose buffering schemes to implement the PCI controller with wide bandwidth and high bus utilization. Also, this paper shows how to verify the PCI controller using real PCI bus environments before its fabrication.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.997-998
• /
• 2006

This paper proposes an design of the OLED(Organic Light Emitting Diodes) driver IC using novel verification method. This method using the HDL(hardware description language) simulator, PLI(Programing Language Interface) and image viewer. The proposed method can be used efficiently to function verification in display driver IC.

• International Journal of Internet, Broadcasting and Communication
• /
• v.14 no.1
• /
• pp.1-9
• /
• 2022

Recently, a large number of cryptocurrencies and block chains have been continuously released. However, these cryptocurrencies and block chains are open to users without authorized verification and testing procedures, causing various reliability problems. Existing cryptocurrencies and blockchain test methods build a blockchain Testnet for a certain period of time by the developer without external verification by a third party, and after repeatedly self-testing and self-operating processes, commercialization is in progress by switching to the Mainnet. This self-verification method does not guarantee objectivity and publicness, and high reliability of customers cannot be realized. This study proposes a cryptocurrency and blockchain test interface and test control system as a third-party open test method.

• 제어로봇시스템학회:학술대회논문집
• /
• 2004.08a
• /
• pp.354-357
• /
• 2004

According to the computerization of railway signaling systems, the interface link between the signaling systems has been replaced by the digital communication channel. At the same time, the importance of the communication link is more pronounced than in the past. In this paper, new network-based protocol for Korean railway signaling has designed between CTC and SCADA system, and the overview of designed protocol is briefly represented. Using the informal method for specifying the communication protocol, a little ambiguity may be contained in the protocol. To clear the ambiguity contained in the designed protocol, we use LTS model to design the protocol for this interface link between CTC and SCADA, the LTS is an intermediate model for encoding the operational behavior of processes. And then, we verify automatically and formally the safety and the liveness properties through the model checking method. Especially, the modal ${\mu}$-calculus, which is a highly expressive method of temporal logic that has been applied to the model checking method. It will be expected to increase the safety, reliability and efficiency of maintenance of the signaling systems by using the designed protocol for railway signaling in Korea.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.40 no.5
• /
• pp.298-305
• /
• 2003

This paper describes a 128-channel hardware simulator that is useful for verification and testing of digital circuits. It performs logic analyzer function and signal generator function at the same time. The core module, which implements one channel of the simulator, operates as a controller with independent memory and internal mode. Therefore, we can easily extend the number of channels with addition of core module. Moreover, since the simulator was implemented as a PC based system, one can construct a low-cost system and can configure convenient GUI(Graphic User Interface) environment. The simulator implemented using FPGA operates at 50Mhz and consumes 55W power as average.