• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.08a
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• pp.12-14
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP). process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. It is well known that the presence of hard and larger size particles in the CMP slurries increases the defect density and surface roughness of the polished wafers. In this paper, we have studied. aging effect the of CMP slurry as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.37-40
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. It is well known that the presence of hard and larger size particles in the CMP slurries increases the defect density and surface roughness of the polished wafers. In this paper, we have studied aging effect the of CMP slurry as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1600-1604
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis of used slurry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.93-96
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis of used slurry.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.158-159
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• 2006

The resistance-capacitance (RC) delay of signals through interconnection materials becomes a big hurdle for high speed operation of semiconductors which contain multilayer interconnection layers. In order to reduce the RC delay, low-k materials will be used for inter-metal dielectric (IMD) materials. We have developed self-consistent simulation tool that includes neutral-species transport model, based on the relaxation continuum (RCT) model. We present the parametric study of the modeling results of a two-frequency capacitively coupled plasma (2f-CCP) with $N_2/H_2$ gas mixture that is known as promising one for organic low-k materials etching. We include the neutral transport model as well as plasma one in the calculation. The plasma and neutrals are calculated self-consistently by iterating the simulation of both species till a spatiotemporal steady state profile could be obtained.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.389-392
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2$-CMP process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and non-uniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between particle size and CMP with particle size analysis of used slurry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.184-187
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) lyaer with free-defect. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. we investigated the performance of $SnO_2-CMP$ process using commonly used silica slurry, ceria slurry, tungsten slurry. This study shows removal rate and nonuniformity of $SnO_2$ thin film used to gas sensor by using Ceria, Silica, W-Slurry after CMP process. This study also shows the relation between partical size and CMP with partical size analysis or used slurry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.731-734
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. Polishing pads play a key role in CMP, which has been recognized as a critical step to improve the topography of wafers for semiconductor fabrication. It is investigated the performance of $SiO_2-CMP$ process using commercial silica slurry as a pad conditioning temperature increased after CMP process. This study also showed the change of SEM images in the pore geometry on the CMP pad surface after use with a different pad conditioning temperature.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.12
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• pp.601-605
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• 2006

The resistance-capacitance (RC) delay of signals through interconnection materials becomes a big hurdle for high speed operation of semiconductors which contain multi-layer interconnections in smaller scales with higher integration density. Low-k materials are applied to the inter-metal dielectric (IMD) materials in order to overcome the RC delay. Relaxation continuum (RCT) model that includes neutral-species transport model have developed to model the etching process in a capacitively coupled plasma (CCP) device. We present the parametric study of the modeling results of a two-frequency capacitively coupled plasma (2f-CCP) with $N_2/H_2$ gas mixture that is known as promising one for organic low-k materials etching. For the etching of low-k materials by $N_2/H_2$ plasma, N and H atoms have a big influence on the materials. Moreover the distributions of excited neutral species influence the plasma density and profile. We include the neutral transport model as well as plasma one in the calculation. The plasma and neutrals are calculated self-consistently by iterating the simulation of both species till a spatio-temporal steady state profile could be obtained.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.31-36
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• 2018

This research scrutinizes the reason of failure after pressure cooker test (PCT) for DRAM device. We use the physical inspecting tools, such as microscope, SEM and TEM, and finally find the discolor phenomenon, corrosion of Al and delamination of inter-metal dielectric (IMD) in the failed devices after PCT. Furthermore, we discover the abnormal $Al_XO_Y$ layer on Al through the careful additional measurements. To find the reason, we evaluate the effect of package ball size and pinhole in passivation layer. Unfortunately, those aren't related to the problems. We also estimate halide effect of Al. The halogens such like Cl are contained within EMC material. Those result in the slight improving of PCT characteristics but do not perfectly solve the problems. We make a hypothesis of Galvanic corrosion. We can find the residue of Ti at the edge of pad open area. We can see the improving the PCT characteristics by the time split of repair etch. The possible mechanism of the PCT failure can be deduced as such following sequence of reactions. The remained Ti reacts on the pad Al by Galvanic corrosion. The ionized Al is easily react with the $H_2O$ supplied under PCT environment, and finally transfers to the abnormal $Al_XO_Y$ layer.