• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.370-373
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical Planarization(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commerical slurries pads, and post-CMP cleaning alternatives are discuess, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper depostion is a mature process from a historical point of view, but a very young process from a CMP persperspective. While copper electrodepostion has been used and stuidied for dacades, its application to Cu damascene wafer processing is only now ganing complete accptance in the semiconductor industry. The polishing mechanism of Cu CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper pasivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.171-175
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectrics and metal, which can apply to employed in integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in inter level dielectrics and metal. Especially, defects like (micro-scratch) lead to severe circuit failure, and affects yield. Current conditioning method - bladder type, orbital pad motion- usually provides unsuitable pad profile during ex-situ conditioning near the end of pad life. Since much of the pad wear occurs by the mechanism of bladder type conditioning and its orbital motion without rotation, we need to implement new ex-situ conditioner which can prevent abnormal regional force on pad caused by bladder-type and also need to rotate the pad during conditioning. Another important study of ADPC is related to the orbital scratch of which source is assumed as diamond grit dropped from the strip during ex-situ conditioning. Scratch from diamond grit damaged wafer severely so usually scraped. Figure 1 shows the typical shape of scratch damaged from diamond. e suspected that intensive forces to the edge area of bladder type stripper accelerated the drop of Diamond grit during conditioning. so new designed Flat stripper was introduced.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 제5회 영호남 학술대회 논문집
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• pp.12-14
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP). process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. It is well known that the presence of hard and larger size particles in the CMP slurries increases the defect density and surface roughness of the polished wafers. In this paper, we have studied. aging effect the of CMP slurry as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

• Journal of electromagnetic engineering and science
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• 제14권4호
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• pp.399-404
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• 2014

A power amplifier (PA) for a femto-cell base station should be highly efficient, linear and small. The efficiency for amplification of a high peak-to-average power ratio (PAPR) signal was improved by designing an asymmetric Doherty PA (DPA). The linearity was improved by applying third-order inter-modulation (IM3) cancellation method. A small size is achieved by designing the DPA using GaN MMIC process. The implemented 2-stage DPA delivers a power-added efficiency (PAE) of 38.6% and a gain of 33.4 dB with an average power of 34.2 dBm for a 7.2 dB PAPR 10 MHz bandwidth LTE signal at 2.14 GHz.

• ETRI Journal
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• 제34권3호
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• pp.388-398
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• 2012

Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multilayer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multilayer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

• ETRI Journal
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• 제33권6호
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• pp.904-913
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die-selection method. The conventional die-selection methods do not result in a high-enough yields of 3D memories because 3D memories are typically composed of known-good-dies (KGDs), which are repaired using self-contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known-bad-die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die-selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die-selection method uses three search-space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die-selection method can significantly improve the yield of 3D memories in various fault distributions.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.37-40
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• 2003

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric (IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Micro-scratches are generated by agglomerated slurry, solidified and attached slurry in pipe line of slurry supply system. It is well known that the presence of hard and larger size particles in the CMP slurries increases the defect density and surface roughness of the polished wafers. In this paper, we have studied aging effect the of CMP slurry as a function of particle size. We prepared and compared the self-developed silica slurry by adding of abrasives before and after annealing. As our preliminary experiment results, we could be obtained the relatively stable slurry characteristics comparable to original silica slurry in the slurry aging effect.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.20-23
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• 2004

As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

• 전기전자학회논문지
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• 제26권3호
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• pp.437-444
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• 2022

본 논문에서는 차량용 반도체에서 CRC 검사를 통해 전송 오류를 검출할 수 있는 SPI 버스 및 I2C 버스를 제안한다. 차량용 반도체에서는 전송에 오류가 발생하여 잘못된 값이 전달되는 경우 치명적인 결과가 발생한다. LIN 버스, CAN 버스와는 다르게 SPI와 I2C 등 구조가 간단한 직렬 인터페이스에서는 전송 오류를 검출하는 방법이 없기 때문에 직렬 인터페이스에 적용할 전송 오류 검출방법을 제시할 필요가 있다. 본 논문에서는 SPI 및 I2C의 통신 프로토콜에 CRC 검사를 사용하여 전송 오류를 검출하는 방법을 제시하고 이를 FPGA로 설계하여 효과적으로 오류를 검출할 수 있음을 검증하였다.

• International journal of advanced smart convergence
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• 제6권1호
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• pp.76-81
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• 2017

This paper presents a low cost and flexible IoT enabled smart LED controller using Arduino that is used for emergency exit signs. The Internet of Things (IoT) is become a global network that put together physical objects using network communications for the purpose of inter-communication of devices, access information on internet, interaction with users as well as permanent connected environment. A crucial point in this paper, is underlined on the potential key points of applying the Arduino platform as low cost, easy to use microcontroller with combination of various sensors applied in IoT technology to facilitate and establishment of intelligent products. To demonstrate the feasibility and effectiveness of the system, devices such as LED strip, combination of various sensors, Arduino, power plug and ZigBee module have been integrated to setup smart emergency exit sign system. The general concept of the proposed system design discussed in this paper is all about the combination of various sensor such as smoke detector sensor, humidity, temperature sensor, glass break sensors as well as camera sensor that are connected to the main controller (Arduino) for the purpose of communicating with LED exit signs displayer and dedicated PC monitors from integrated system monitoring (controller room) through gateway devices using Zig bee module. A critical appraisal of the approach in the area concludes the paper.