• Title/Summary/Keyword: Intellectual Property Core

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A Study on How to Vitalize Technical Innovation of the Small and Medium Firms Utilizing Regional Innovation System (지역혁신기관을 활용한 중소기업 기술혁신 활성화 방안에 관한 연구)

  • Jeon, Gi-Sang;No, Gyu-Seong;Lee, Seung-Hui
    • 한국디지털정책학회:학술대회논문집
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    • 2006.12a
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    • pp.19-41
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    • 2006
  • The purpose of this paper is to suggest field-oriented policy of regional innovation support system. To accomplish this purpose, we examined the status quo of technical support ,performance satisfaction of consumers and practical issues. The key factors influencing core technical innovation of small and medium firms are development fund, R&D employees, experimental instrument, technical information, protection of intellectual property, subcontracting and so on. To make sure of practical effect, therefore, it would rather necessary to implement policy support linking government and supporting means on the ground of needs of small and medium firms than specific method such as funding.

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Parameterized Soft IP Design of Complex-number Multiplier Core (복소수 승산기 코어의 파라미터화된 소프트 IP 설계)

  • 양대성;이승기;신경욱
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.10B
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    • pp.1482-1490
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    • 2001
  • 디지털 통신 시스템 및 신호처리 회로의 핵심 연산블록으로 사용될 수 있는 복소수 승산기 코어의 파라미터화된 소프트 IP (Intellectual Property)를 설계하였다. 승산기는 응용분야에 따라 요구되는 비트 수가 매우 다양하므로, 승산기 코어 IP는 비트 수를 파라미터화하여 설계하는 것이 필요하다. 본 논문에서는 복소수 승산기의 비트 수를 파라미터화 함으로써 사용자의 필요에 따라 승수와 피승수를 8-b∼24-b 범위에서 2-b 단위로 선택하여 사용할 수 있도록 하였으며, GUI 환경의 코어 생성기 PCMUL_GEN는 지정된 비트 크기를 갖는 복소수 승산기의 VHDL 모델을 생성한다. 복소수 승산기 코어 IP는 redundant binary (RB) 수치계와 본 논문에서 제안하는 새로운 radix-4 Booth 인코딩/디코딩 회로를 적용하여 설계되었으며, 이를 통해 기존의 방식보다 단순화된 내부 구조와 고속/저전력 특성을 갖는다. 설계된 IP는 Xilinx FPGA로 구현하여 기능을 검증하였다.

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Design of Self-Timed Standard Library and Interface Circuit

  • Jung, Hwi-Sung;Lee, Moon-Key
    • Proceedings of the IEEK Conference
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    • 2000.07a
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    • pp.379-382
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    • 2000
  • We designed a self-timed interface circuit for efficient communication in IP (Intellectual Property)-based system with high-speed self-timed FIFO and a set of self-timed event logic library with 0.25um CMOS technology. Optimized self-timed standard cell layouts and Verilog models are generated for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. With clock control method and FIFO, we implemented high-speed 32bit-interface chip for self-timed system, which generated maximum system clock is 2.2GHz. The size of the core is about 1.1mm x 1.1mm.

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A Study on How to vitalize Technical Innovation of the Small and Medium Firms (중소기업 기술혁신 활성화 방안 연구)

  • Lee, Seung-Hee;Noh, Kyoo-Sung;Kim, Hye-Kyung;Park, Lae-Gyu
    • Journal of Digital Convergence
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    • v.5 no.1
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    • pp.101-116
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    • 2007
  • The purpose of this paper is to suggest field-oriented policy of regional innovation support system. To accomplish this purpose, we examined the status quo of technical support, performance satisfaction of consumers and practical issues. The key factors influencing core technical innovation of small and medium firms are development fund, R&D employees, experimental instrument, technical information, protection of intellectual property, subcontracting and so on. To make sure of practical effect, therefore, it would rather necessary to implement policy support linking government and supporting means on the ground of needs of small and medium firms than specific method such as funding.

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A Study on the Logic Design of Multi-Display Driver (멀티 디스플레이 구동 드라이버 로직 설계에 관한 연구)

  • Jin K.C.;Chun K.J.;Kim S.H.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2005.10a
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    • pp.212-215
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    • 2005
  • The needs of larger screen in mobile device would be increased as the time of ubiquitous and convergence is coming. And, the type of mobile device has been evolved from bar, slide to row. Recently, the study on the multi-display screen which has seamless gap between two display panel has been published, and moreover the System On Chip(SOC) design strategy of core chip has been the most promising Field-Programmable Gate Array(FPGA) technology in the display system. Therefore, in this paper, we proposed the design technique of SOC and evaluated the effectiveness with Very high speed Hardware Description Language(VHDL) Intellectual Property (IP) for the operation of multi display device driver. Also, This IP design would be to allow any kind of user interface in control system.

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Ensure intellectual property rights for 3D pringting 3D modeling design (딥러닝 인공지능을 활용한 사물인터넷 비즈니스 모델 설계)

  • Lee, Yong-keu;Park, Dae-woo
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2016.10a
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    • pp.351-354
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    • 2016
  • The competition of Go between AlphaGo and Lee Sedol attracted global interest leading AlphaGo to victory. The core function of AlphaGo is deep-learning system, studying by computer itself. Afterwards, the utilization of deep-learning system using artificial intelligence is said to be verified. Recently, the government passed the loT Act and developing its business model to promote loT. This study is on analyzing IoT business environment using deep-learning AI and constructing specialized business models.

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Classification of NFT Security Issues and Threats through Case Analysis

  • Mi-Na, Shim
    • International Journal of Internet, Broadcasting and Communication
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    • v.15 no.1
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    • pp.23-32
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    • 2023
  • Since NFTs can be used like certificates due to the nature of blockchain, their use in various digital asset trading markets is expanding. This is because NFTs are expected to be actively used as a core technology of the metaverse virtual economy as non-transferable NFTs are developed. However, concerns about NFT security threats are also growing. Therefore, the purpose of this study is to investigate and analyze NFT-related infringement cases and to clearly understand the current security status and risks. As a research method, we determined NFT security areas based on previous studies and analyzed infringement cases and threat types for each area. The analysis results were systematically mapped in the form of domain, case, and threat, and the meaning of the comprehensive results was presented. As a result of the research, we want to help researchers clearly understand the current state of NFT security and seek the right research direction.

The introduction of a criminal case arbitration on premise the civil and commercial arbitration (민상사(民商事) 중재제도(仲裁制度)를 전제(前提)로 한 형사중재제도(刑事仲裁制度)의 도입방안(導入方案))

  • Nam, Seon-Mo
    • Journal of Arbitration Studies
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    • v.19 no.3
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    • pp.93-119
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    • 2009
  • Nowadays the number of crimes is increasing rapidly and society is getting more and more dangerous. Recently the criminal aspect of our society, the intelligence, diversity, localized area, as well as for the crime victims also difficult to predict the damage recovery is not easy to change their level of pain and are also serious. This phenomenon is increasingly expected to intensify, the proper response is a factory. The more so if the victim of murder. The criminal mediation working on the operational adjustments Borrower payment, Construction charges, investments and financial transactions due to interpersonal conflicts that occurred as a fraud, embezzlement, breach of trust property crimes such accused, individuals between the defamatory, offensive, encroachment, violating intellectual property rights and private Disputes about the complaint case and other criminal disputes submitted to mediation to resolve it deems relevant to the case who are accused. But the core of a detective control adjustment, adjust the members' representative to the region, including front-line player or a lawyer appointed by the attorney general at this time by becoming parties to this negative view may be ahead. Some scholars are criticizing the current criminal justice system for the absence of proper care for the criminal victims, as an alternative to the traditional criminal justice system. The introduction of the summary trial and related legal cases, the command structure, compensation system, crime victims' structural system can be seen as more classify, crime subject to victim's complaint, By case with a criminal misdemeanor in addition to disagree not punish criminal, minor offense destination, traffic offenders, regular property crime, credit card theft, intellectual property rights violators can be seen due to more categories can try. They sued in law enforcement, Prosecution case has been received and if any one party to the criminal detective Arbitration request arbitration by the parties can agree to immediately contact must be referred to arbitration within 15 days of when the arbitration case will be dismissed. These kinds of early results of the case related to, lawyers are involved directly in the arbitration shall be excluded. Arbitration system is the introduction of criminal justice agencies working to help resolve conflicts caused by adjustment problems will be able to. This article does not argue that we should stick to the traditional justice system as a whole. Instead it argues that the restrictive role of the traditional justice is to be preserved.

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Educational Needs of the Core Competencies for Low-Carrier Technology Teachers (초임 기술교사를 위한 핵심 역량의 추출과 교육 요구도 분석)

  • Choi, Yuhyun
    • 대한공업교육학회지
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    • v.44 no.1
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    • pp.209-231
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    • 2019
  • The purpose of this study was to extract the factors of core competency required for technology teachers and to analyze the educational needs for extracted core competency factors and to search for the application of core competencies in the in-service technology teachers education. This study was conducted by literature review, expert validation, and needs assessment method. The survey was conducted by 92 low-carrier technology teachers who participated in in-service technology teachers education for upgrading to first grade teacher certificate. Data were analyzed the factor analysis, needs assessment, and IPA analysis using SPSS 24. The core competencies with high education needs were selected by the score of the Borich formula and the IPA analysis. As a result of the study, 29 factors of core competencies were chosen as the priority: challenge, planning ability, decision making ability, future orientation, intellectual property utilization ability, communication ability, and creative thinking etc. Based on the conclusions of this study, I would suggest the following. It is to create a new in-service education program reflected on core competencies that have high educational needs of low-carrier technology teachers. In addition, a strategy that reflects core competencies methodically in existing in-service teachers education program is needed. Future research should be followed by research on curriculum design to enhance high needed core competencies of low-carrier technology teachers.

A Study of CPC-based Technology Classification Analysis Model of Patents (CPC 기반 특허 기술 분류 분석 모델)

  • Chae, Soo-Hyeon;Gim, Jangwon
    • The Journal of the Korea Contents Association
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    • v.18 no.10
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    • pp.443-452
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    • 2018
  • With the explosively increasing intellectual property rights, securing technological competitiveness of companies is more and more important. In particular, since patents include core technologies and element technologies, patent analysis researches are actively conducted to measure the technological value of companies. Various patent analysis studies have been conducted by the International Patent Classification(IPC), which does not include the latest technical classification, and the technical classification accuracy is low. In order to overcome this problem, the Cooperative Patent Classification(CPC), which includes the latest technology classification and detailed technical classification, has been developed. In this paper, we propose a model to analyze the classification of the technologies included in the patent by using the detailed classification system of CPC. It is possible to analyze the inventor's patents in consideration of the relation, importance, and efficiency between the detailed classification schemes of the CPCs to extract the core technology fields and to analyze the details more accurately than the existing IPC-based methods. Also, we perform the comparative evaluation with the existing IPC based patent analysis method and confirm that the proposed model shows better performance in analyzing the inventor's core technology classification.