• The Journal of the Korea institute of electronic communication sciences
• /
• v.8 no.1
• /
• pp.99-104
• /
• 2013

As a demand for the portable device requiring smaller size and better performance is in hike, reducing the size of conventionally used planar 2 dimensional integration circuit(IC) cannot be a solution for the enhancement of the semiconductor integration circuit technology due to an increase in RC delay among interconnects. To address this problem, a new technology of 3 dimensional integration circuit (3D-IC) has been developing. In this study, three-dimensional integrated device was investigated due to improve of reducing the size, interconnection problem, high system performance and functionality.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.1495-1498
• /
• 2008

We proposed driving method with variable integration time for ambient light sensing. One operation period of the proposed driving method consists of several sub-integration periods with variable integration time which can enlarge dynamic range of ambient light sensing circuit. Temperature dependent characteristic of p-intrinsic-metal (p-i-m) diode can be compensated using the proposed driving method.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2004.08a
• /
• pp.75-80
• /
• 2004

By the SOG (System-on-Glass) technology with excimer laser anneal process, the number of IC chips and the area of the mounted IC chips on the printed circuit board are reduced. In new circuit integrations on the glass substrate, we have developed D/A converter including the new capacitor array, amplifier comprising the original comparators and new display device with capturing images by integrated sensor into a pixel. This paper discusses the application of circuit integration of low-temperature poly-Si.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.26 no.11
• /
• pp.1666-1671
• /
• 1989

A novel switched-capacitor circuit for interfacing capacitive microtransducers with a digital system is developed based on the dual-slope integration. It consists of a differential integrator and a comparator. Driven by the teo phase clock, the circuit first senses the capacitance difference between the transducer and the reference capacitor in the form of charge, and accumulates it into the feedback capabitor of the integrator for a fixed period of time. The resulant accumulated charge is next extracted by the known reference charge until the integrator output voltage refurns to zero. The length of time required for the integrator output to return to zero, as measured by the number of clock cycle gated into a counter is proportional to the capacitance difference, averaged over the integration period. The whole operation is insensitive to the reference voltage and the capacitor values involved in the circuit, Thus the proposed circuit permits an accurate differental capacitance measurement. An error analysis has showh that the resolution as high as 8 bits can be expected by realizing the circuit in a monolithic MOS IC form. Besides the accuracy, it features the small device count integrable onto a small chip area. The circuit is thus particularly suitadble for the on-chip interface.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.28A no.1
• /
• pp.46-51
• /
• 1991

The new signal process circuit using ISFETs as two input devices of a MOS differential amplifier stage for application to a ISFET biosensor was developed and its operational characteristics simulated. For a single chip integration of ISFETs, developed signal process circuit and metal reference electrode, serial studies including process development and chip layout was carried out.

• Smart Structures and Systems
• /
• v.14 no.6
• /
• pp.1131-1150
• /
• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• Proceedings of the KSME Conference
• /
• 2001.11b
• /
• pp.523-528
• /
• 2001

There are many difficult problems in analyzing the flow characteristics in a high voltage circuit breaker such as shock wave and complex geometries, which may be either static or in relative motion. Although a variety of mesh generation techniques are now available, the generation of meshes around complicated, multicomponent geometries like a gas circuit breaker is still a tedious and difficult task for the computational fluid dynamics. This paper presents the computational method for analyzing the compressible flow fields in a high voltage gas circuit breaker using the Cartesian cut-cell method based on the CFD-CAD integration, which can achieve the accurate representation of the geometry designed by a CAD tools. The technique is frequently satisfied, and it will be almost universally so in the future, as the CFD-CAD traffic increases.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.191-194
• /
• 2000

A level of integration will increase, if the number of elements of the circuit can be reduced. We aim to design the circuit of the new system for any further integration by using Neuron MOS Transistor. In this paper, we consider to introduce Soft-Hardware Logic and multiple-valued logic to the design methods for reducing the number of elements and inner wiring. We have designed 4-valued add-subtracter circuit using above logic. We discuss the design methods, features, and characteristics of this circuit by SPICE simulation.

• Proceedings of the KIEE Conference
• /
• 2001.10a
• /
• pp.30-32
• /
• 2001

There are many difficult problems in analyzing the flow characteristics in a high voltage circuit breaker such as shock wave and complex geometries, which may be either static or in relative motion. Although a variety of mesh generation techniques are now available, the generation of meshes around complicated, multi-component geometries like a gas circuit breaker is still a tedious and difficult task for the computational fluid dynamics. This paper presents the CFD program for analyzing the compressible flow fields in a high voltage gas circuit breaker using the Cartesian cut-cell method based on the CFD-CAD integration, which can achieve the accurate representation of the geometry designed by a CAD tools. This technique is frequently satisfied, and it will be almost universally so in the future, as the CFD-CAD traffic increase.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.1635-1639
• /
• 2006

LTPS has potential capability to realize various kinds of circuit integrations on panel glass because of its relatively higher field effect mobility of around 100cm2/Vs. Recent progress of LTPS technologies and advanced technologies, which are generally called "System on Glass (SOG)," will be discussed. The technology includes circuit integration, photo-sensor integration for input functions, and display quality and performance improvement.