• Journal of the Korean Society for Precision Engineering
• /
• v.15 no.10
• /
• pp.103-112
• /
• 1998

The evolution of semiconductor manufacturing technology has accelerated the reduction of device dimensions and the increase of integrated circuit density. In order to improve yield within a short turn around time and maintain it at high level, a system that can rapidly determine problematic processing steps is needed. The statistical process control detects abnormal process variation of key parameters. Expert systems in SPC can serve as a valuable tool to automate the analysis and interpretation of control charts. A set of IF-THEN rules was used to formalize knowledge base of special causes. This research proposes a strategy to apply expert system to SPC in semiconductor manufacturing. In analysis, the expert system accomplishes the instability detection of process parameter, In diagnosis, an engineer is supported by process analyzer program. An example has been used to demonstrate the expert system and the process analyzer.

• Journal of the Microelectronics and Packaging Society
• /
• v.9 no.3
• /
• pp.1-6
• /
• 2002

A low temperature process technology of copper thin films has been developed by a chemical vapor deposition technology for multi-level metallzations in ULSI fabrication. The copper films were deposited on TiN/Si substrates in helium atmosphere with the substrate temperature between $130^{\circ}C$ and $250^{\circ}C$. In order to get more reliable metallizations, effects on the post-annealing treatment to the electrical properties of the copper films have been investigated. The Cu films were annealed at the $5 \times10^{-6}$ Torr vacuum condition and the electrical resistivity and the nano-structures were measured for the Cu films. The electrical resistivity of Cu films shown to be reduced by the post-annealing. The electrical resistivity of 2.0 $\mu \Omega \cdot \textrm{cm}$ was obtained for the sample deposited at the substrate temperature of $180^{\circ}C$ after vacuum annealed at $300^{\circ}C$. The resistivity variations of the films was not exactly matched with the size of the nano-structures of the copper grains, but more depended on the contamination of the copper films.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.2
• /
• pp.83-88
• /
• 2015

Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.3
• /
• pp.175-180
• /
• 2003

As the integrated circuit device shrinks to the deep submicron regime, the ion implantation process with high ion dose has been attracted beyond the conventional ion implantation technology. In particular, for the case of boron ion implantation with low energy and high dose, the stabilization and throughput of semiconductor chip manufacturing are decreasing because of trouble due to the machine conditions and beam turning of ion implanter system. In this paper, we focused to the improved characteristics of processing conditions of ion implantation equipment through the modified deceleration mode. Thus, our modified recipe with low energy and high ion dose can be directly apply in the semiconductor manufacturing process without any degradation of stability and throughput.

• Journal of the Korea Society for Simulation
• /
• v.11 no.2
• /
• pp.17-29
• /
• 2002

There is an increasing interest in high-performance A/D(Analog-to-Digital) converters for use in integrated analog and digital mixed processing systems. Pipeline A/D converter architectures coupled with BiCMOS process technology have the potential for realizing monolithic high-speed and high-accuracy A/D converters. In this paper, the design of 12bit pipeline BiCMOS A/D converter presented. A BiCMOS operational amplifier and comparator suitable for use in the pipeline A/D converter. Test/simulation results of the circuit blocks and the converter system are presented. The main features is low distortion track-and-hold with 0-300MHz input bandwidth, and a proprietary 12bit multi-stage quantizer. Measured value is DNL=${\pm}$0.30LSB, INL=${\pm}$0.52LSB, SNR=66dBFS and SFDR=74dBc at Fin=24.5MHz. Also Fabricated on 0.8um BiCMOS process.

• Proceedings of the Korean Society of Computer Information Conference
• /
• 2014.01a
• /
• pp.77-79
• /
• 2014

본 논문에서는 Arduino의 I2C 통신을 통해 인터랙티브한 악기를 제안한다. 각각의 큐브는 서로를 인식하고 인식 후 집단이 된 큐브들은 하나의 악기가 된다. Arduino의 통신 핀을 알루미늄 호일에 연결하여 다른 큐브와 접촉 시 통신이 될 수 있도록 하였다. 통신이 이룬 큐브들을 rgbLED 색상 변화를 통해 시각적으로 접촉/비접촉을 나타냈다. 또한 Processing을 통해 그룹이 된 큐브들의 악기 소리를 제어하였다.

• Proceedings of the IEEK Conference
• /
• 2002.06a
• /
• pp.417-420
• /
• 2002

In this paper, we implemented a SDH synchronous network system based on ITU-T recommendation G.707 - Network node interface for the synchronous digital archy(SDH). For the system, we used signal processing SDH ASIC, and designed a FPGA_Control chip for various signal control and a FPGA_Alignment cllip for data alignment using YHDL(Very high speed integrated circuit Hardware Description Language). For system monitoring, an operation system was developed using ANSI C and executed in CPU (Motorola MPC-860). The system was evaluated by using ANT-20 for data transmission error defection, jitter detection, pointer chocking, and overhead determination.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.6
• /
• pp.58-70
• /
• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.4
• /
• pp.251-257
• /
• 2015

This work presents modelling and simulation of a readout integrated circuit (ROIC) design considering pair-wise serial configuration along with thermal modeling of an uncooled microbolometer array. A fully differential approach is used at the input stage in order to reduce fixed pattern noise due to the process variation and self-heating-related issues. Each pair of microbolometers is pulse-biased such that they both fall under the same self-heating point along the self-heating trend line. A ${\pm}10%$ process variation is considered. The proposed design is simulated with a reference input image consisting of an array of $127{\times}92$ pixels. This configuration uses only one unity gain differential amplifier along with a single 14-bit analog-to-digital converter in order to minimize the dynamic range requirement of the ROIC.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3190-3192
• /
• 1999

A Novel wide-band wide-tunable current-mode (CM) gamma corrector for HDTV camera applications is proposed. The gamma corrector provides accurate gamma control in a wide range by simple electrical adjustment of weighting amplifiers' gain. It has wide signal bandwidth more than 40MHz sufficient for HDTV video signal processing and is implementable with simple integrated circuit with low power dissipation of 125mW.