• Title/Summary/Keyword: Integrated circuit processing

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The Cu-CMP's features regarding the additional volume of oxidizer (산화제 배합비에 따른 연마입자 크기와 Cu-CMP의 특성)

  • Kim, Tae-Wan;Lee, Woo-Sun;Choi, Gwon-Woo;Seo, Young-Jin
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.20-23
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    • 2004
  • As the integrated circuit device shrinks to the smaller dimension, the chemical mechanical polishing(CMP) process was required for the global planarization of inter-metal dielectric(IMD) layer with free-defect. However, as the IMD layer gets thinner, micro-scratches are becoming as major defects. Chemical-Mechanical polishing(CMP) of conductors is a key process in Damascene patterning of advanced interconnect structure. The effect of alternative commercial slurries pads, and post-CMP cleaning alternatives are discuss, with removal rate, scratch dentisty, surface roughness, dishing, erosion and particulate density used as performance metrics. Electroplated copper deposition is a mature process from a historical point of view, but a very young process from a CMP perspective. While copper electro deposition has been used and studied for decades, its application to Cu damascene wafer processing is only now gaining complete acceptance in the semiconductor industry. The polishing mechanism of Cu-CMP process has been reported as the repeated process of passive layer formation by oxidizer and abrasion action by slurry abrasives. however it is important to understand the effect of oxidizer on copper passivation layer in order to obtain higher removal rate and non-uniformity during Cu-CMP process. In this paper, we investigated the effects of oxidizer on Cu-CMP process regarding the additional volume of oxidizer.

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A Study on the Implementation of Digital Filters with Reduced Memory Space and Dual Impulse Response Types (기억용량 절약과 순회방식 선택이 가능한 디지털 필터의 구성에 관한 연구)

  • Park, In Jung;Rhee, Tae Won
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.6
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    • pp.950-956
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    • 1986
  • In this paper, a direct addressing mode of a microprocessor is introduced to save memory capacity, and also a dedicated digital filter is constructed to speed up the filter processing and to enable an easy selection of the impulse response types. A theoretical analysis has been conducted on the errors caused by the finite word klength, rounding-off and multiplication procedures. The digital filter designed by the proposed method is made into a module which can function as a 7th-order recursive or a 14-order nonrecursive type with a simples witch operation. The proposed filter is implemented on a printed-circuit board. The frequency characteristics of this filter can be controlled by the multiplication values stored in ROMs. A low-pass, a high-pass and a band-pass filter have been designed and their frequency characteristics are verified by actual measurements. For a order higher filer, two filter modules have been cascaded into an integrated filter of 23rd-order non-recursive low-pass type and a 12th-order recursive multiband type. Their frequency characteirstics have been found to agree with the theory.

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Long range-based low-power wireless sensor node

  • Komal Devi;Rita Mahajan;Deepak Bagai
    • ETRI Journal
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    • v.45 no.4
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    • pp.570-580
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    • 2023
  • Sensor nodes are the most significant part of a wireless sensor network that offers a powerful combination of sensing, processing, and communication. One major challenge while designing a sensor node is power consumption, as sensor nodes are generally battery-operated. In this study, we proposed the design of a low-power, long range-based wireless sensor node with flexibility, a compact size, and energy efficiency. Furthermore, we improved power performance by adopting an efficient hardware design and proper component selection. The Nano Power Timer Integrated Circuit is used for power management, as it consumes nanoamps of current, resulting in improved battery life. The proposed design achieves an off-time current of 38.17309 nA, which is tiny compared with the design discussed in the existing literature. Battery life is estimated for spreading factors (SFs), ranging from SF7 to SF12. The achieved battery life is 2.54 years for SF12 and 3.94 years for SF7. We present the analysis of current consumption and battery life. Sensor data, received signal strength indicator, and signal-to-noise ratio are visualized using the ThingSpeak network.

A Study on the Pixel-Paralled Image Processing System for Image Smoothing (영상 평활화를 위한 화소-병렬 영상처리 시스템에 관한 연구)

  • Kim, Hyun-Gi;Yi, Cheon-Hee
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.11
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    • pp.24-32
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    • 2002
  • In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

Development of T-commerce Processing Payment Module Using IC Credit Card(EMV) (IC신용카드(EMV)를 이용한 T-커머스 결제처리 모듈 개발)

  • Choi, Byoung-Kyu;Lee, Dong-Bok;Kim, Byung-Kon;Heu, Shin
    • The KIPS Transactions:PartA
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    • v.19A no.1
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    • pp.51-60
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    • 2012
  • IC(Integrated circuits)card, generally be named smard card, embedded MPU(Micro Processor Unit) of small-size, memory, EEPROM, Card Operating System(COS) and security algorithm. The IC card is used in almost all industry such as a finance(credit, bank, stock etc.), a traffic, a communication, a medical, a electronic passport, a membership management and etc. Recently, a application field of IC card is on the increase by method for payments of T-commerce, as T-commerce is becoming a new growth engine of the broadcating industry by trend of broadcasting and telecommunication convergence, smart mechanization of TV. For example, we can pay in IC credit card(or IC cash card) on T-Commerce. or we can be provided TV banking service in IC cash card such as ATM. However, so far, T-commerce payment services have weakness in security such as storage and disclosure of card information as well as dropping sharply about custom ease because of taking advantage of card information input method using remote control. To solve this problem, This paper developed processing payment module for implementing TV electronic payment system using IC credit card payment standard, EMV.

Education Equipment for FPGA Design of Sensor-based IOT System (센서 기반의 IOT 시스템의 FPGA 설계 교육용 장비)

  • Cho, Byung-woo;Kim, Nam-young;Yu, Yun-seop
    • Journal of Practical Engineering Education
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    • v.8 no.2
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    • pp.111-120
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    • 2016
  • Education equipment for field programmable gate array (FPGA) design of sensor-based IOT (Internet Of Thing) system is introduced. Because sensors have different interfaces, several types of interface controller on FPGA need. Using this equipment, several types of interface controller, which can control ADC (analog-to-digital converter) for analog sensor outputs and $I^2C$ (Inter-Integrated Circuit), SPI (Serial Peripheral Interface Bus), and GPIO (General-Purpose Input/Output) for digital sensor outputs, can be designed on FPGA. Image processing hardware using image sensors and display controller for real and image-processed images or videos can be design on FPGA chip. This equipment can design a SOC (System On Chip) consisting of a hard process core on Linux OS and a FPGA block for IOT system which can communicate with wire and wireless networks. Using the education equipment, an example of hardware design using image sensor and accelerometer is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs.

QUANTITATIVE MONITORING OF TISSUE OXYGENATION BY TIME-RESOLVED SPECTROSCOPY

  • Yamashita, Yutaka;Oda, Motoki;Ohmae, Etsuko;Tsuchiya, Yutaka
    • Proceedings of the Korean Society of Near Infrared Spectroscopy Conference
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    • 2001.06a
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    • pp.2101-2101
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    • 2001
  • Near-infrared spectroscopy is now being used in clinical diagnosis as a non-invasive monitor of tissue oxygenation state. However, due to lack of the optical pathlength information within tissues, it is still difficult to quantitate the hemoglobin concentration with present CW techniques. Time-resolved spectroscopy (TRS), which measures temporal profiles of emerging light from tissues, enables to estimate the pathlength distribution within tissues by converting time to distance. Consequently, quantitative measurement of tissue oxygenation is possible by analyzing the data with optical diffusion equation 1) or our Microscopic Beer-Lambert law2). Time-Resolved Spectroscopy System : TRS-1O3) Our TRS-10 system consists of a three-wavelength (759, 797, 833 nm) PLP as pulsed light source, a high speed PMT with high sensitivity and three signal-processing circuits for time-resolved measurement (CFD/TAC, A/D converter and histogram memory). Optical pulse train consisting of 759, 797 and 833nm is generated by PLP at 5㎒ repetition rate and irradiated a sample through a single optical fiber. The diffuse-reflected light from the sample is collected by a bundle fiber and then detected by the PMT for single photon measurement. After being amplified by a following fast amplifier, the electrical signals for each wavelength are picked out by CFD/TAC module. Then, a signal processing circuit integrated the TRS data for each wavelength individually. The simultaneous TRS measurement for three wavelengths achieved without any optical or mechanical switch. Experiment and Results Input and detection fibers of TRS-10 were attached at the human forehead with a fiber separation of 3cm. TRS measurements were continuously performed for about 20 minutes including 2 minutes hyper ventilation. It was observed that the total hemoglobin concentration was decreasing during the hyper ventilation and recovered until 2 minutes after hyper ventilation. On the other hand, the deoxy-hemoglobin concentration began to increase after hyper ventilation and had its peak at around 2 minute later, showing 502 drop from 75% to 60% due to inhibition of breathing by performing hyper ventilation. The results showed that this system might be able to quantitate the concentrations of oxy- and deoxy-hemoglobin in the human brain.

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A Neural Metwork's FPGA Realization using Gate Level Structure (게이트레벨 연산구조를 사용한 신경합의 FPGA구현)

  • Lee, Yun-Koo;Jeong, Hong
    • Journal of Korea Multimedia Society
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    • v.4 no.3
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    • pp.257-269
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    • 2001
  • Because of increasing number of integrated circuit, there is many tries of making chip of neural network and some chip is exit. but this is not prefer because YLSI technology can't support so large hardware. So imitation of whole system of neural network is more prefer. There is common procedure in signal processing as in the neural network and pattern recognition. That is multiplication of large amount of signal and reading LUT. This is identical with some operation of MLP, and need iterative and large amount of calculation, so if we make this part with hardware, overall system's velocity will be improved. So in this paper, we design neutral network, not neuron which can be used to many other fields. We realize this part by following separated bits addition method, and it can be appled in the real time parallel process processing.

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Design of Programmable SC Filter (프로그램 가능한 SC Filter의 설계)

  • 이병수;이종악
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.11 no.3
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    • pp.172-178
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    • 1986
  • The recent interest in the design of filters is motivatied by the fact that such filter can be fully integrated using standard metal-oxide-semiconductor processing technology. This is due to replacing all the resistors in the active RC filter network by the switched capacitors. The voltage gain of a SC filter depends only on the rations of capacitance and these ratios can be obtained and maintained to high accuracy. Therefore, it is known that a switched capacitor is much better than a resistor in temperature and linearity characteristics. This paper proposed a programmable SC filter and proved the fact that ${omega}_0$ Q and G of this circuit can be controlled by digital signal. Experiments show that SC filter remains the low sensitivities but it can't avoid little influence of parasitic capacitance. As the transfer characteristic of the SC filter is varied with sampling frequency and resistor array, SC filtering technigue can be applied for digital processing, speech analysis and synthesis and so on.

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Design and Implementation of the Digital Neuron Processor for the real time object recognition in the making Automatic system (생산자동화 시스템에서 실시간 물체인식을 위한 디지털 뉴런프로세서의 설계 및 구현)

  • Hong, Bong-Wha;Joo, Hae-Jong
    • Journal of the Korea Society of Computer and Information
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    • v.12 no.3
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    • pp.37-50
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    • 2007
  • In this paper, we designed and implementation of the high speed neuron processor for real time object recognition in the making automatic system. and we designed of the PE(Processing Element) used residue number system without carry propagation for the high speed operation. Consisting of MAC(Multiplication and Accumulation) operator using residue number system and sigmoid function operator unit using MAC(Mixed Radix conversion) is designed. The designed circuits are descript by C language and VHDL(Very High Speed Integrated Circuit Hardware Description Language) and synthesized by compass tools and finally, the designed processor is fabricated in $0.8{\mu}m$ CMOS process. we designed of MAC operation unit and sigmoid proceeding unit are proved that it could run time 0.6nsec on the simulation and improved to the speed of the three times and decreased to hardware size about 50%, each order. The designed neuron processor can be implemented of the object recognition in making automatic system with desired real time processing.

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