• 제목/요약/키워드: Integrated Flight Instruction

검색결과 2건 처리시간 0.016초

기본비행훈련장치(BATD)의 효율적 활용과 비행교육 효과 분석 (The Effective Use of Basic Aviation Training Device (BATD) andthe Analysis of Flight Training Effectiveness)

  • 장동관;권문진
    • 한국항공운항학회지
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    • 제30권3호
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    • pp.117-122
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    • 2022
  • A method to increase the effectiveness of flight training at a low cost by applying the correct flight training method to students without flight experience is a very important factor. BATD equipped with an extended display device enables the proper cross-check of external references and internal instruments by integrated flight instruction methods, enabling effective flight training in the initial stages. In addition, BATD employs the Cessna 172 model with Glass Cockpit to help make it easy to apply to actual flights. As a result of analyzing the effect of flight training through a survey of students who completed the BATD practice lecture, it was very helpful to understand the theories related to flight that they had already learned, and they responded that they could easily adapt to all flight subjects in additional FTD practice lectures. Therefore, a well-planned BATD practice lecture will be easy to adapt to real flight training, which will have significant effects in reducing time and cost.

최신 프로세서 탑재 비행제어 컴퓨터의 통합시험을 위한 프로세서 모니터링 연구 (A Study on Processor Monitoring for Integration Test of Flight Control Computer equipped with A Modern Processor)

  • 이철;김재철;조인제
    • 제어로봇시스템학회논문지
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    • 제14권10호
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    • pp.1081-1087
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    • 2008
  • This paper describes limitations and solutions of the existing processor-monitoring concept for a military supersonics aircraft Flight Control Computer (FLCC) equipped with modern architecture processor to perform the system integration test. Safecritical FLCC integration test, which requires automatic test for thousands of test cases and real-time input/output test condition generation, depends on the processor-monitoring device called Processor Interface (PI). The PI, which relies upon on the FLCC processor's external address and data-bus data, has some limitations due to multi-fetching capability of the modern sophisticated military processors, like C6000's VLIW (Very-Long Instruction Word) architecture and PowerPC's Superscalar architecture. Several techniques for limitations were developed and proper monitoring approach was presented for modem processor-adopted FLCC system integration test.