• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.11
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• pp.2708-2716
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• 2013

This paper presents implementation of embedded remote monitoring diagnosis system which has effective wireless channel structure and communication protocols with user-friendly UI for intelligent digital vessel. Developed system contains integrated vessel monitoring system, server, exclusive mobile terminal and smart phone. We designed an effective dual structure communication channel and simple but effective communication protocol on the monitoring system. Failures of the wireless communication are minimized and the wrong wireless communication channel is immediately replaced. In addition, we developed an effective embedded Linux UI for LCD. The implemented wireless monitoring system was tested and verified on digital vessel.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.33 no.3
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• pp.261-264
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• 2009

We present a three-dimensional (3D) particle focusing channel using the positive dielectrophoresis (pDEP) guided by a dielectric structure between two planar electrodes. The dielectric structure between two planar electrodes induces the maximum electric field at the center of the microchannel, and particles are focused to the center of the microchannel by pDEP as they flow from the single sample injection port. Compared to the previous 3D particle focusing methods, the present device achieves the simple and effective particle focusing function without any additional fluidic ports and top electrodes. In the experimental study, approximately 90 % focusing efficiency were achieved within the focusing length of 2mm, on both x-z plane (top-view) and y-z plane (side-view) for $2{\mu}m$-diameter polystyrene (PS) bead at the applied voltage over 15 Vp-p (square wave) and at the flow rate below 0.01 ${\mu}l$/min. The present 3D particle focusing channel results in a simple particle focusing method suitable for use in integrated microbiochemical analysis system.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.8 s.251
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• pp.722-730
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• 2006

In this study, the flow characteristics of a FPN (Fountain Pen Nano-Lithography) using active membrane pumping are investigated. The FPN has integrated chamber, micro channel, and high capacity reservoir for continuous ink feed. The most important aspect in this probe provided control of fluid injection using active membrane pumping in chamber. The flow rates in channel by capillary force are theoretically analyzed, including the control of the mass flow rates by the deflection of the membrane. The above results are compared with the numerical simulations that calculated by commercial code, FLUENT. The velocity of the fluid in micro channel shows linear behaviors. And the mass flows are proportional to the second order function of the pumping pressure that is imposed to the membrane.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.5
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• pp.338-347
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• 2005

A computer-based low back muscle evaluation system was designed to simultaneously acquire, process, display, quantify, and correlate electromyographic(EMG) activity with muscle force, and range of motion(ROM) in the lumbar muscle of human. This integrated multi-channel system was designed around notebook PC. Each channel consisted of a time and frequency domain block, and T-F(time-frequency) domain block. The captured data in each channel was used to display and Quantify : raw EMG, histogram, zero crossing, turn, RMS(root mean square), variance, mean, power spectrum, median frequency, mean frequency, wavelet transform, Wigner-Ville distribution, Choi-Williams distribution, and Cohen-Posch distribution. To evaluate the performance of the designed system, the static and dynamic contraction experiments from lumbar(waist) level of human were done. The experiment performed in five subjects, and various parameters were tested and compared. This system could equally well be modified to allow acquisition, processing, and analysis of EMG signals in other studies and applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.421-424
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• 2004

As the deep sub-micron devices are recently integrated high package density, novel process method for sub $0.1{\mu}m$ devices is required to get the superior thin gate oxide characteristics and reliability. However, few have reported on the electrical quality and reliability on the thin gate oxide. In this paper I will recommand a novel shallow trench isolation structure for thin gate oxide $30{\AA}$ of deep sub-micron devices. Different from using normal LOCOS technology, novel shallow trench isolation have a unique 'inverse narrow channel effects' when the channel width of the devices is scaled down shallow trench isolation has less encroachment into the active device area. Based on the research, I could confirm the successful fabrication of shallow trench isolation(STI) structure by the SEM, in addition to thermally stable silicide process was achiever. I also obtained the decrease threshold voltage value of the channel edge and the contact resistance of $13.2[\Omega/cont.]$ at $0.3{\times}0.3{\mu}m^2$. The reliability was measured from dielectric breakdown time, shallow trench isolation structure had tile stable value of $25[%]{\sim}90[%]$ more than 55[sec].

• ETRI Journal
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• v.46 no.2
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• pp.323-332
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• 2024

Receiver and transmitter monolithic microwave integrated circuit (MMIC) multifunction chips (MFCs) for active phased-array antennas for Ka-band satellite communication (SATCOM) terminals have been designed and fabricated using a 0.15-㎛ GaAs pseudomorphic high-electron mobility transistor (pHEMT) process. The MFCs consist of four-channel radio frequency (RF) paths and a 4:1 combiner. Each channel provides several functions such as signal amplification, 6-bit phase shifting, and 5-bit attenuation with a 44-bit serial-to-parallel converter (SPC). RF pads are implemented on the bottom side of the chip to remove the parasitic inductance induced by wire bonding. The area of the fabricated chips is 5.2 mm × 4.2 mm. The receiver chip exhibits a gain of 18 dB and a noise figure of 2.0 dB over a frequency range from 17 GHz to 21 GHz with a low direct current (DC) power of 0.36 W. The transmitter chip provides a gain of 20 dB and a 1-dB gain compression point (P1dB) of 18.4 dBm over a frequency range from 28 GHz to 31 GHz with a low DC power of 0.85 W. The P1dB can be increased to 20.6 dBm at a higher bias of +4.5 V.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.3
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• pp.35-40
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• 2024

In this paper, the design, implementation, and analysis of a device capable of transmitting and receiving millimeter-wave signals and performing channel sounding measurements in atmospheric conditions at distances of up to approximately 10km outdoors are presented. The device is expected to be instrumental in studying the propagation characteristics of millimeter-wave frequencies. Utilizing data such as received power levels and power delay profiles (PDPs), comparisons with predicted values using path loss, K-factor, and other propagation models are facilitated. The mobile transceiver unit, integrated onto a vehicle platform, allows for flexible adjustment of transmitter and receiver positions, while synchronization issues with distance are mitigated using a rubidium atomic clock. Furthermore, automatic boresight alignment using scanning techniques is employed to locate the main sector of the antenna.

• ETRI Journal
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• v.46 no.4
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• pp.708-715
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• 2024

We propose a 10-GHz 2 × 2 phased-array radio frequency (RF) receiver with an 8-bit linear phase and 15-dB gain control range using 65-nm complementary metal-oxide-semiconductor technology. An 8 × 8 phased-array receiver module is implemented using 16 2 × 2 RF phased-array integrated circuits. The receiver chip has four single-to-differential low-noise amplifier and gain-controlled phase-shifter (GCPS) channels, four channel combiners, and a 50-Ω driver. Using a novel complementary bias technique in a phase-shifting core circuit and an equivalent resistance-controlled resistor-inductor-capacitor load, the GCPS based on vector-sum structure increases the phase resolution with weighting-factor controllability, enabling the vector-sum phase-shifting circuit to require a low current and small area due to its small 1.2-V supply. The 2 × 2 phased-array RF receiver chip has a power gain of 21 dB per channel and a 5.7-dB maximum single-channel noise-figure gain. The chip shows 8-bit phase states with a 2.39° root mean-square (RMS) phase error and a 0.4-dB RMS gain error with a 15-dB gain control range for a 2.5° RMS phase error over the 10 to10.5-GHz band.

• The Magazine of the IEIE
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• v.37 no.8
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• pp.50-59
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• 2010

$0.18-{\mu}m$ high voltage technology 13.5V high voltage well-based symmetric EDMOS isolated by MTI was designed and fabricated. Using calibrated process and device model parameters, the characteristics of the symmetric and asymmetric EDMOS have been simulated. The asymmetric EDMOS has higher performance, better $R_{sp}$ / BVDSS figure-of-merit, short-channel immunity and smaller pitch size than the symmetric EDMOS. The asymmetric EDMOST is a good candidate for low-power and smaller source driver chips. The low voltage logic well-based EDMOS process has advantages over high voltage well-based EDMOS in process cost by eliminating the process steps of high-voltage well/drift implant, high-temperature long-time thermal steps, etc. The specific on-resistance of our well-designed logic well-based EDMOSTs is compatible with the smallest one published. TCAD simulation and measurement results show that the improved logic well-based nEDMOS has better electrical characteristics than those of the conventional one. The improved EDMOS proposed in this paper is an excellent candidate to be integrated with low voltage logic devices for high-performance low-power low-cost chips.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.10
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• pp.894-900
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• 2006

This paper reports the fabrication and characterization of $32{\times}32$ thermal cantilever array for nano-scaled memory device applications. The $32{\times}32$ thermal cantilever array with integrated tip heater has been fabricated with micro-electro-mechanical systems(MEMS) technology on silicon on insulator(SOI) wafer using 9 photo masking steps. All of single-level cantilevers(1,024 bits) have a p-n junction diode in order to eliminate any electrical cross-talk between adjacent cantilevers. Nonlinear electrical characteristic of fabricated thermal cantilever shows its own thermal heating mechanism. In addition, n-channel high-voltage MOSFET device is integrated on a wafer for embedding driver circuitry.