• Title/Summary/Keyword: Integrated Cache Management System

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Development of A Web-cache System with Compression Capability (압축 기능을 가진 웹캐시 시스템 개발)

  • Park, Zin-Won;Kim, Myung-Kyun;Hong, Yoon-Hwan
    • The KIPS Transactions:PartA
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    • v.11A no.1
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    • pp.29-36
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    • 2004
  • As the number of Internet users and the amount of web contents have increased very fast, reducing the load of web servers and providing web services more rapidly have been great issues. A web-cache system, which is located between the user and the web server, has been used by many web service providers as an effective way to reduce the load of web servers and the web service response time. In this paper, we have developed a web-cache system which is based on the Squid cache and has a compression capability. The web-cache system in which compression capability reduces the amount of network traffic and the web service response time by transfering the web contents in the compressed format over the network between the web-cache system and the user. The performance enhancement is greater in the reverse-cache system than in the forward-cache system because in the case of the reverse-cache system, the cache reduces the amount of traffic on the Internet which is the bottleneck in the network path between the user and the web server. The experimentation result shows that the amount of data traffic has reduced from 2 to 8 times depending on the size of the web contents. The web server response time has reduced 37% on the average and when the size of the web content is greater than 10Kbyte, the response time has reduced 87% on the average.

An Efficient Address Mapping Table Management Scheme for NAND Flash Memory File System Exploiting Page Address Cache (페이지 주소 캐시를 활용한 NAND 플래시 메모리 파일시스템에서의 효율적 주소 변환 테이블 관리 정책)

  • Kim, Cheong-Ghil
    • Journal of Digital Contents Society
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    • v.11 no.1
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    • pp.91-97
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    • 2010
  • Flash memory has been used by many digital devices for data storage, exploiting the advantages of non-volatility, low power, stability, and so on, with the help of high integrity, large capacity, and low price. As the fast growing popularity of flash memory, the density of it increases so significantly that its entire address mapping table becomes too big to be stored in SRAM. This paper proposes the associated page address cache with an efficient table management scheme for hybrid flash translation layer mapping. For this purpose, all tables are integrated into a map block containing entire physical page tables. Simulation results show that the proposed scheme can save the extra memory areas and decrease the searching time with less 2.5% of miss ratio on PC workload and can decrease the write overhead by performing write operation 33% out of total writes requested.

A Reconfigurable, General-purpose DSM-CC Architecture and User Preference-based Cache Management Strategy (재구성이 가능한 범용 DSM-CC 아키텍처와 사용자 선호도 기반의 캐시 관리 전략)

  • Jang, Jin-Ho;Ko, Sang-Won;Kim, Jung-Sun
    • The KIPS Transactions:PartC
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    • v.17C no.1
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    • pp.89-98
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    • 2010
  • In current digital broadcasting systems, GEM(Globally Executable MHP)-based middlewares such as MHP(Multimedia Home Platform), OCAP(OpenCable Application Platform), ACAP(Advanced Common Application Platform) are the norm. Despite much of the common characteristics shared, such as MPEG-2 and DSM-CC(Digital Storage Media-Command and Control) protocols, the information and data structures they need are slightly different, which results in incompatibility issues. In this paper, in line with an effort to develop an integrated DTV middleware, we propose a general-purpose, reconfigurable DSM-CC architecture for supporting various standard GEM-based middlewares without code modifications. First, we identify DSM-CC components that are common and thus can be shared by all GEM-based middlewares. Next, the system is provided with middleware-specific information and data structures in the form of XML. Since the XML information can be parsed dynamically at run time, it can be interchanged either statically or dynamically for a specific target middleware. As for the performance issues, the response time and usage frequency of DSM-CC module highly contribute to the performance of STB(Set-Top-Box). In this paper, we also propose an efficient application cache management strategy and evaluate its performance. The performance result has shown that the cache strategy reflecting user preferences greatly helps to reduce response time for executing application.

Development of Communication Module for a Mobile Integrated SNS Gateway (모바일 통합 SNS 게이트웨이 통신 모듈 개발)

  • Lee, Shinho;Kwon, Dongwoo;Kim, Hyeonwoo;Ju, Hongtaek
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39B no.2
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    • pp.75-85
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    • 2014
  • Recently, mobile SNS traffic has increased tremendously due to the deployment of smart devices such as smart phones and smart tablets. In this paper, mobile integrated SNS gateway is proposed to cope with massive SNS traffic. Most of mobile SNS applications update the information with individual connection to the corresponding servers. The proposed gateway integrates these applications. It is for reducing SNS traffic caused by continuous data request and improving the mobile communication performance. The key elements of the mobile integrated SNS gateway are the synchronization, cache and integrated certification. The proposed protocol and gateway system have implemented on the testbed which deployed on the real network to evaluate the performance of the proposed gateway. Finally, we present the caching performance of gateway system implementation.

Analysis on the Temperature of Multi-core Processors according to Placement of Functional Units and L2 Cache (코어 내부 구성요소와 L2 캐쉬의 배치 관계에 따른 멀티코어 프로세서의 온도 분석)

  • Son, Dong-Oh;Kim, Jong-Myon;Kim, Cheol-Hong
    • Journal of the Korea Society of Computer and Information
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    • v.19 no.4
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    • pp.1-8
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    • 2014
  • As cores in multi-core processors are integrated in a single chip, power density increased considerably, resulting in high temperature. For this reason, many research groups have focused on the techniques to solve thermal problems. In general, the approaches using mechanical cooling system or DTM(Dynamic Thermal Management) have been used to reduce the temperature in the microprocessors. However, existing approaches cannot solve thermal problems due to high cost and performance degradation. However, floorplan scheme does not require extra cooling cost and performance degradation. In this paper, we propose the diverse floorplan schemes in order to alleviate the thermal problem caused by the hottest unit in multi-core processors. Simulation results show that the peak temperature can be reduced efficiently when the hottest unit is located near to L2 cache. Compared to baseline floorplan, the peak temperature of core-central and core-edge are decreased by $8.04^{\circ}C$, $8.05^{\circ}C$ on average, respectively.