• Title/Summary/Keyword: Instruction code

Search Result 145, Processing Time 0.02 seconds

Static Timing Analysis Tool for ARM-based Embedded Software (ARM용 내장형 소프트웨어의 정적인 수행시간 분석 도구)

  • Hwang Yo-Seop;Ahn Seong-Yong;Shim Jea-Hong;Lee Jeong-A
    • Journal of KIISE:Computing Practices and Letters
    • /
    • v.11 no.1
    • /
    • pp.15-25
    • /
    • 2005
  • Embedded systems have a set of tasks to execute. These tasks can be implemented either on application specific hardware or as software running on a specific processor. The design of an embedded system involves the selection of hardware software resources, Partition of tasks into hardware and software, and performance evaluation. An accurate estimation of execution time for extreme cases (best and worst case) is important for hardware/software codesign. A tighter estimation of the execution time bound nay allow the use of a slower processor to execute the code and may help lower the system cost. In this paper, we consider an ARM-based embedded system and developed a tool to estimate the tight boundary of execution time of a task with loop bounds and any additional program path information. The tool we developed is based on an exiting timing analysis tool named 'Cinderella' which currently supports i960 and m68k architectures. We add a module to handle ARM ELF object file, which extracts control flow and debugging information, and a module to handle ARM instruction set so that the new tool can support ARM processor. We validate the tool by comparing the estimated bound of execution time with the run-time execution time measured by ARMulator for a selected bechmark programs.

Run-time Memory Optimization Algorithm for the DDMB Architecture (DDMB 구조에서의 런타임 메모리 최적화 알고리즘)

  • Cho, Jeong-Hun;Paek, Yun-Heung;Kwon, Soo-Hyun
    • The KIPS Transactions:PartA
    • /
    • v.13A no.5 s.102
    • /
    • pp.413-420
    • /
    • 2006
  • Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. We already addressed how to efficiently assign data to multi-memory banks in our previous work. This paper reports on our recent attempt to optimize run-time memory. The run-time environment for dual data memory banks (DBMBs) requires two run-time stacks to control activation records located in two memory banks corresponding to calling procedures. However, activation records of two memory banks for a procedure are able to have different size. As a consequence, dual run-time stacks can be unbalanced whenever a procedure is called. This unbalance between two memory banks causes that usage of one memory bank can exceed the extent of on-chip memory area although there is free area in the other memory bank. We attempt balancing dual run-time slacks to enhance efficiently utilization of on-chip memory in this paper. The experimental results have revealed that although our algorithm is relatively quite simple, it still can utilize run-time memories efficiently; thus enabling our compiler to run extremely fast, yet minimizing the usage of un-time memory in the target code.

Development of an Editor and Howling Engine for Realtime Software Programmable Logic Controller based on Intelligent Agents (지능적 에이전트에 의한 실시간 소프트웨어 PLC 편집기 및 실행엔진 개발)

  • Cho, Young-In
    • Journal of KIISE:Software and Applications
    • /
    • v.32 no.12
    • /
    • pp.1271-1282
    • /
    • 2005
  • Recently, PC-based control is incredibly developed in the industrial control field, but it is difficult for PLC programming in PC. Therefore, I need to develop the softeware PLC, which support the international PLC programming standard(IECl131-3) and can be applied to diverse control system by using C language. In this paper, I have developed the ISPLC(Intelligent Agent System based Software Programmable Logic Controller). In ISPLC system, LD programmed by a user which is used over $90\%$ among the 5 PLC languages, is converted to IL, which is one of intermediate codes, and IL is converted to the standard C rode which can be used in a commercial editor such as Visual C++. In ISPLC, the detection of logical error in high level programming(C) is more eaier than PLC programming itself The study of code conversion of LD->IL->C is firstly tried in the world as well as KOREA. I developed an execution engine with a good practical application. To show the effectiveness of the developed system, 1 applied it to a practical case, a real time traffic control(RT-TC) system. ISPLC is minimized the error debugging and programming time owing to be supported by windows application program.

Reading Cognitive Culture by Intentional Instruction and Convergence Analysis in Advertising Content Stories (광고콘텐츠 스토리에 담긴 의도적인 지시체와 융복합적 해석소에 의한 인지적 문화읽기)

  • Lim, Ji-Won
    • Journal of Korea Entertainment Industry Association
    • /
    • v.13 no.2
    • /
    • pp.37-45
    • /
    • 2019
  • The This study aimed at clarifying that the cognitive interpretation code is essential for college students to read the correct culture while discussing the producer's story production system for creative advertising content and the process of interpreting the meaning of advertisers and the formation of principles and beliefs. The production of advertising content aimed at persuasion should first identify anachronistic reason system based on the target audience's perception principle. A concise analysis of the experiment found key clues that confirmed that a sample of the producer's intended story would be inconsistent with the clues of information that a college student could remember. I have tried to organize a semantic analysis tool that combines these key clues and as a tool for reading culture of the right time for college students. As a result, university student inmates were able to identify one side of positive communication: reading a new cognitive symbol culture based on their subjective experience and beliefs, rather than analyzing cross-sectional analysis of the primary language and non-verbal expressions of their advertising contents. In the future, if an advertising content story producer works to identify such a process in advance, it will help persuade inmates.

Cloning and Transcription Analysis of Sporulation Gene (spo5) in Schizosaccharomyces pombe (Schizosaccharomyces bombe 포자형성 유전자(spo5)의 Cloning 및 전사조절)

  • 김동주
    • The Korean Journal of Food And Nutrition
    • /
    • v.15 no.2
    • /
    • pp.112-118
    • /
    • 2002
  • Sporulation in the fission yeast Schizosaccharomyces pombe has been regarded as an important model of cellular development and differentiation. S. pombe cells proliferate by mitosis and binary fission on growth medium. Deprivation of nutrients especially nitrogen sources, causes the cessation of mitosis and initiates sexual reproduction by matting between two sexually compatible cell types. Meiosis is then followed in a diploid cell in the absence of nitrogen source. DNA fragment complemented with the mutations of sporulation gene was isolated from the S. pombe gene library constructed in the vector, pDB 248' and designated as pDB(spo5)1. We futher analyzed six recombinant plasmids, pDB(spo5)2, pDB(spo5)3, pDB(spo5)4, pDB(spo5)5, pDB (spo5)6, pDB(spo5)7 and found each of these plasmids is able to rescue the spo5-2, spo5-3, spo5-4, spo5-5, spo5-6, spo5-7 mutations, respectively. Mapping of the integrated plasmid into the homologous site of the S. pombe chromosomes demonstrated that pDB(spo5)1, and pDB(spu5)Rl contained the spo5 gene. Transcripts of spo5 gene were analyzed by Northern hybridization. Two transcripts of 3.2 kb and 2.5kb were detected with 5kb Hind Ⅲ fragment containing a part of the spo5 gene as a probe. The small mRNA(2.5kb) appeared only when a wild-type strain was cultured in the absence of nitrogen source in which condition the large mRNA (3.2kb) was produced constitutively. Appearance of a 2.5kb spo5-mRNA depends upon the function of the meil, mei2 and mei3 genes.