• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.376-379
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• 2001

In this paper, I design the control chip that controls inner test sequence of Logic Tester to test chip. Logic tester has the thirteen inner instructions to control test sequence in test. And these instructions are saved in memory with test pattern data. Control chip generates address and control signal such as read, write signal of memory. Before testing, necessary data such as start address, end address, etc. are written to inner register of control chip. When test started, control chip receives the instruction in start address and executes, and generates address and control signals to access tester' inner memory. So whole test sequence is controlled by making the address and control signal in tester's inner memory. Control chip designs instruction's execution blocks, respectively. So if inner instruction is added from now on, a revision is easy. The control chip will be made using FPGA of Xilinx Co. in future.

• The KIPS Transactions:PartA
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• v.11A no.3
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• pp.163-172
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• 2004

Multimedia applications tend to access their data as a streaming pattern with regular intervals. This characteristic can be utilized in prefetching the multimedia data into cache memory so as to reduce their execution speeds. The reference-prediction prefetch algorithm predicts the memory address that seems to be used in the next time based on the previous history of memory references stored in the prediction reference table. This paper proposes a strategy to manipulate the reference prediction table which contains all of the data reference instructions to scalar and streaming data. We have recognized that the scalar reference instructions do not contribute to the data prefetching algorithm. Therefore, when replacing an element in the reference prediction table, the proposed algorithm preferentially selects the scalar reference instruction before the stream reference instruction. It makes the stream reference instruction to stay for a long time compared to the FIFO replacement policy, and eventually improves the performance of data prefetching.

• Journal of Korean Library and Information Science Society
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• v.22
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• pp.139-169
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• 1995

The purpose of this study is to analyze the search pattern and search outcome of the National Central Library OPAC users by measuring their success rates and identifying the factors of failure and the personal background which bring about the differences of the search outcome. Various methods have been used for the study. Personal interview was used to find the pattern of the search, observation method was used to investigate the search process and the failure factors, and a questionnaire was used to survey personal background of searchers. The data were collected during the period of 7 days from April 17, 1995 through April 23, 1995. The search of 1, 217 cases, sampling systematically 25% out of the whole users, were collected and analyzed for the study. The findings of the study can be summarized as follows : First, in regard to the pattern, known-item search(72.6%) was preferred to the subject search(27.4%) and in case of known-item search the access point used were in the order of title, author, title and author. Second, the overall success rate of known-item search was 50.3% and the success rates were in order of author and date, title, and author. The failure factors of known-item search were divided into users factor of 67% and the database factor of 33%, respectively. Third, in case of subject search, its overall success rate was 44.1% and the keyword was the major access point, and the average of precision ratio was very low. Fourth, the analysis of the personal background related to the search outcome has shown significant differences by sex, the experience of using OPAC, education level, and the frequency of using other information retrieval systems. Based on the results the following suggestions can be made to improve the search outcome : First, the system should be su n.0, pplemented online help function to assist users to overcome the failure during search. Second, user instruction in group or individual should be implemented for the users to understand the system.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.11
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• pp.658-672
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• 2004

Multimedia applications are required to process the huge amount of data at high speed in real time. The memory reference instructions such as loads and stores are the main factor which limits the high speed execution of processor. To enhance the memory reference speed, cache prefetch schemes are used so as to reduce the cache miss ratio and the total execution time by previously fetching data into cache that is expected to be referenced in the future. In this study, we present an advanced data cache prefetching scheme that improves the conventional RPT (reference prediction table) based scheme. We considers the cache line size in calculation of the address stride referenced by the same instruction, and enhances the prefetching algorithm so that the effect of prefetching could be maintained even if an irregular address stride is inserted into the series of uniform strides. According to experiment results on multimedia benchmark programs, the cache miss ratio has been improved 29% in average compared to the conventional RPT scheme while the bus usage has increased relatively small amount (0.03%).