• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.2562-2567
• /
• 2005

This paper suggests a new method discretization of nonlinear system using Taylor series expansion and zero-order hold assumption. This method is applied into the sampled-data representation of a nonlinear system with input time delay. Additionally, the delayed input is time varying and its amplitude is bounded. The maximum time-delayed input is assumed to be two sampling periods. Them mathematical expressions of the discretization method are presented and the ability of the algorithm is tested for some of the examples. And 'hybrid' discretization scheme that result from a combination of the ‘scaling and squaring' technique with the Taylor method are also proposed, especially under condition of very low sampling rates. The computer simulation proves the proposed algorithm discretized the nonlinear system with the variable time-delayed input accurately.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.41 no.6
• /
• pp.39-46
• /
• 2004

One of the significant issues in cluster analysis is to identify a proper number of clusters hidden under given data. In this paper we propose a novel approach to systematically determine the number of clusters based on Input Representation Coverage (IRC), which is newly defined as a quantified value of how well original input data in Gaussian feature space can be captured with a certain number of clusters. Furthermore, its usability and applicability is also investigated via experiments with synthetic data. Our experiment results show that the proposed approach is quite useful in approximately finding the real number of clusters implicitly contained in the data.

• Journal of Electrical Engineering and information Science
• /
• v.3 no.1
• /
• pp.28-35
• /
• 1998

In this paper, an NxN input-buffered crosspoint packet switch which selects a Head of the Line, HOL, packet in contention randomly is analyzed with a new approach. The approach is based on both a Markov chain representation of the input buffer and the probability that a HOL packet is successfully served. The probability as a function of N is derived, and it makes it possible to express the average packet delay and the average number of packets in the buffer as a function of N. The contention resolution policy based on the occupancy of the input buffer is also presented and analyzed with this same approach and the relationship between two selection policies is analyzed in terms of the occupancy of the input buffer.

• 제어로봇시스템학회:학술대회논문집
• /
• 2001.10a
• /
• pp.93.3-93
• /
• 2001

We propose the cascade PID type fuzzy control method for a good performance such as robustness. The one of proposed method, the first stage have two input variables of an error and a derivative error, and one output variable, and the next stage have two input variables of the output of first stage and an integral error, and one output variable, have two stages. The other, the first stage has one input of an error, and one output variable, and the second stage have two input of the output of first stage and a derivative error, and one output variable, and the third stage have two input of the output of the second stage and an integer error, and one output variable ...

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.12
• /
• pp.64-70
• /
• 1994

In this paper, we inverstigated how a parricular internal inverter circuit, which is located far from the input protection in CMOS DRAM, can be easily damaged by external ESD stress, while the protection circuit remains intact. It is shown in a mega bit DRAM that the internal circuit can be safe from ESD by simply improving the input protection circuit. An inverter, which consists of a relatively small NMOSFET and a very large PMOSFET, is used to speed up DRAMs, and the small NMOSFET is vulnerable to ESD in case that the discharge current beyond the protection flows through the inverter to Vss or Vcc power lines on chip. This internal circuit damage can not be detected by only measuring input leakage currents, but by comparing the standby and on operating current before and after ESD stressing. It was esperimentally proven that the placement of parasitic bipolar transistor between input pad and power supply is very effective for ESD immunity.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.10
• /
• pp.19-26
• /
• 1997

Novel class AB CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well CMOS process for high-frequency current-mode signal processing were developed. The CCII for low power operation consists of a class AB push-pull stage for the current input, a complementary source follower for the voltage input, and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated CCII show that the current input impedance is 875.ohm. and the bandwidth of flat gain when used as a voltage amplifier extends beyond 4MHz. The power dissipation is 1.25mW and the active chip area is 0.2*0.15[mm$\^$2/].

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.137-140
• /
• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

• Journal of Institute of Control, Robotics and Systems
• /
• v.7 no.4
• /
• pp.281-287
• /
• 2001

In this paper, we deal with a decentralized control scheme with input compensation form for gantry crane systems. By considering the gantry cranes characteristics, the system is decentralized into two subsystems, the travelling and swaying subsystem and the hoisting subsystem. For decentralizing the system, a simple algorithm is proposed using the observability canonical form. The decentralized subsystems include unknown inputs that one coupled with other subsystems and actuator failures. These unknown input and actuator failures are estimated by using PI observation techniques. And those estimated values are used to construct an input compensation form. Finally, the proposed decentralized control scheme for the gantry crane systems is verified by crane simulation.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.29 no.1
• /
• pp.9-17
• /
• 2006

This paper considers a six sigma project for improving productivity of the brace complement center pillar. The project follows a disciplined process of fife phases: define, measure, analyze, improve, and control. A process map is used to identify process input and output variables. Eleven key process input variables are selected by using X&Y matrix and FMEA, and finally eight vital few input variables are selected from analyze phase. The optimum process conditions of the vital few input variables are jointly obtained by maximizing productivity of the brace complement center pillar using DOE and alternative selection method.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.367-370
• /
• 2000

It is shown that $I_{DDQ}$ testing is very useful for shipping fault-free CMOS ICs. However, test time of $I_{DDQ}$ testing is extremely larger than one of logic testing. In this paper, a new test input sequence generation methodology is proposed to reduce the test time of $I_{DDQ}$ testing. At first, it is Shown that $I_{DDQ}$ test time Will be denominated by charge supply current for load capacitance of gates whose output logic values are changed by test input vector application and the charge current depends on input sequence of test vectors. After that, a test input sequence generation methodology is proposed. The feasibility is checked by some experiments.riments.