• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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• pp.481-484
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• 2003

A strategy for a torque ripple reduction drive of single-phase SRM with high power factor is proposed. The drive for switched reluctance motor (SRM) is presented to achieve sinusoidal, near unity power factor input current with low torque ripple. The proposed SRM drive has no additional active switch. And a single-stage approach, which combines a DC link capacitor used as dc source and a drive used for driving the motor into one power stage, has a simple structure and low cost. The characteristics and validity of the proposed circuit is discussed in depth through the experimental results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.959-962
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• 2004

A strategy for a torque ripple reduction drive of single-phase SRM with high power factor is proposed. The drive for switched reluctance motor (SRM) is presented to achieve sinusoidal, near unity power factor input current with low torque ripple. The proposed SRM drive has no additional active switch. And a single-stage approach, which combines a DC link capacitor used as do source and a drive used for driving the motor into one power stage, has a simple structure and low cost. The characteristics and validity of the proposed circuit is discussed in depth through the experimental results.

• Journal of Power Electronics
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• 제12권4호
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• pp.528-537
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• 2012

This paper presents an interleaved resonant converter with a parallel-series transformer connection in order to achieve ripple current reduction at the output capacitor, zero voltage turn-on for the active switches, zero current turn-off for the rectifier diodes, less voltage stress on the rectifier diodes, and less current stress on the transformer primary windings. The primary windings of the two transformers are connected in parallel in order to share the input current and to reduce the root-mean-square (rms) current on the primary windings. The secondary windings of the two transformers are connected in series in order to ensure that the transformer primary currents are balanced. A full-wave diode rectifier is used at the output side to clamp the voltage stress of the rectifier diode at the output voltage. Two circuit modules are operated with the interleaved PWM scheme so that the input and output ripple currents are reduced. Based on the resonant behavior, all of the active switches are turned on under zero voltage switching (ZVS), and the rectifier diodes are turned off under zero current switching (ZCS) if the operating switching frequency is less than the series resonant frequency. Finally, experiments with a 1kW prototype are described to verify the effectiveness of the proposed converter.

• Journal of Power Electronics
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• 제12권4호
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• pp.643-653
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• 2012

An interleaved DC/DC converter with series-connected transformers is presented to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two half-bridge converter cells connected in series to reduce the voltage stress of the switches at one-half of the input voltage. The output sides of the two converter cells with interleaved pulse-width modulation are connected in parallel to reduce the ripple current at the output capacitor and to achieve load current sharing. Therefore, the size of the output chokes and the capacitor can be reduced. The output capacitances of the MOSFETs and the resonant inductances are resonant at the transition instant to achieve ZVS turn-on. In addition, the switching losses on the power switches are reduced. Finally, experiments on a laboratory prototype (24V/40A) are provided to demonstrate the performance of the proposed converter.

• Journal of Power Electronics
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• 제18권4호
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• pp.955-964
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• 2018

In this paper, an active capacitor-diode-switch (CDS) snubber is proposed for L-type current-fed isolated DC-DC converters. The proposed CDS-clamped converter has a number of advantages. It can achieve wide range zero-voltage switching (ZVS) on two switches, a continuous input current with a low ripple, a reduction of one active switch and high efficiency. The operating principles, analysis and parameter design guideline are presented. A 300 W prototype is built to test the proposed converter. Simulation and experimental results are shown at 30 V input voltage and 400 V output voltage.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.207-209
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• 2019

This paper proposes a grid-tied photovoltaic (PV) system, consisting of Voltage-fed dual-active-bridge (DAB) dc-dc converter with single phase inverter. The proposed converter allows a small dc-link capacitor, so that system reliability can be improved by replacing electrolytic capacitors with film capacitors. The double line frequency free maximum power point tracking (MPPT) is also realized in the proposed converter by using Ripple Correlation method. First of all, to eliminate the double line frequency ripple which influence the reduction of DC source capacitance, control is developed. Then, a designing of Current control in DQ frame is analyzed and to fulfill the international harmonics standards such as IEEE 519 and P1547, $3^{rd}$ harmonic in the grid is directly compensated by the feedforward terms generated by the PR controller with the grid current in stationary frame to achieve desire Total Harmonic Distortion (THD). 5-kW PV converter and inverter module with a small dc-link film capacitor was built in the laboratory with the proposed control and MPPT algorithm. Experimental results are given to validate the converter performance.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 전력전자학술대회 논문집
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• pp.407-408
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• 2013

본 논문은 주파수 제어를 통한 인터리브드 DC-DC 컨버터의 입력 전류 리플 최소화 알고리즘을 제안한다. 제안하는 알고리즘은 시스템을 전류 불연속 모드에서 0.33 또는 0.67의 고정 듀티로 제어하여 입력전류 리플을 저감한다. 제안한 알고리즘을 3상 부스트 컨버터에 적용하고 그 타당성을 실험 및 시뮬레이션을 통해 검증한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.90-92
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• 2002

This paper presents an improved C-Dump converter system for switched reluctance motors(SRM). The proposed C-Dump converter derived from the conventional converter for SRM. The proposed converter could overcome the limitation of the conventional C-Dump converter, and could reduce the whole cost of the SRM system since the voltage stress of the dump switch $T_d$ is reduced to $V_{dc}$ when compared with $2V_{dc}$ for the conventional C-Dump converter. The attractive features of the proposed converters are; high-efficient and low-cost, elimination of dump inductor, simple control strategy, smaller size arid light weight. The proposed converter is able to be fast magnetization by $2V_{dc}$, which is sum of the input voltage and charging voltage of the dump capacitor. Also, this topology has many advantages such as freewheeling of phase winding without complex control, reduction of current ripple, reduction of torque ripple, and reduction of switching frequency. Simulation demonstrates the good performance of the converter.

• Journal of Power Electronics
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• 제9권2호
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• pp.173-179
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• 2009

This paper proposes a new three-phase diode rectifier system with a sinusoidal input current at unity power factor and a regulated and isolated output voltage at low level. The inherent natural wave-shaping capability of the reduced kVA polyphase transformer together with an active current wave-shaping technique results in a significant reduction of input and output filter requirements associated with switching ripple and EMI. The operation principles are described along with a design example and a comparative evaluation. Experimental results on a 1.5kW prototype are provided to validate the proposed concept.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제48권9호
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• pp.517-522
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• 1999

This paper addresses the issue of current sampling in a high performance AC drive system fed by a discontinuous PWM inverter. The effect of the sampling error due to the measurement delay produced by an input stage low pass filter and an A/D converter is described in the case of discontinuous PWM. To compensate for the sampling error, a method to estimate the delay time of the whole measurement system based on the measured current is proposed and its effectiveness is verified by experimental results. The proposed algorithm can automatically estimate the system delay introduced by the low pass filter and the A/D converter at the commissioning stage. By delaying the current sampling by the estimated value, experimental results indicate that more than 50% reduction of current ripple can be achieved.