• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.12
• /
• pp.63-70
• /
• 2013

This paper describes a high PSRR low-dropout(LDO) linear regulator for wide frequency range without output-capacitor. Owing to both of the cascode compensation technique and the current buffer compensation technique in nested Miller compensation loop, the proposed LDO not only maintaines high stability but also achieves high PSRR over wide frequency range with reasonable on-chip capacitances. Since the external capacitor is removed by the proposed compensation techniques, the cost for pad is eliminated. The designed LDO works under the input voltage range from 2.5V to 4.5V and provides up to 10mA load current with the output voltage of 1.8V. The LDO was implemented with 0.18um CMOS technology and the area is 300um X 120 um. The measured power supply rejection ratio(PSRR) is -76dB and -43dB at DC and 1MHz, respectively. The operating current is 25uA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.10a
• /
• pp.103-106
• /
• 2012

A memory access method that data are read with different sequences with writing order is a simple but important procedure in many image compression standards, such as JPEG, MPEG1/2/4, H.264, and HEVC. For real time processing, double buffering is widely used using two block sized buffers, that accesses buffers concurrently with alternative way to read and write. In some cases like a transpose memory in 2D DCT with a simple and regular access order, a single buffering which requires only single block sized buffer can be used. This paper shows that even in complex access orders there is a regularity among updating orders within a finite turns, and suggested an effective implementation method using a single block sized buffer to process concurrent read/write operation with different access orders.

• Journal of KIISE:Computing Practices and Letters
• /
• v.5 no.4
• /
• pp.385-394
• /
• 1999

제품을 설계하는 디자이너나 엔지니어는 많은 시간과 노력을 들이지 않고서 그들이 설계한 3차원 제품 모델에 대한 사실적인 이미지를 원한다. 디자인 프로세스의 초기인 개념 설계에서부터 설계검증, 그리고 가공 과정에서 사실적인 이미지가 매우 유용하므로, 대부분의 주요 CAD 제작사는 그들의 CAD 소프트웨어에 고급 렌더링 기능을 추가하고 있다. 상용의 CAD/CAM 모델러에서는 NURB 곡면을 기초로 모델링을 수행하므로, NURB 곡면을 렌더링할 수 있는 패키지가 필요하다. VIF(Visual InterFace) 렌더링 라이브러리는 A-buffer 방식과 Ray tracing 방식의 두 가지 고급 렌더링 모드를 제공한다. 다각형은 물론 NURB 곡면을 입력으로 받아 사용자가 설정한 표면의 각종 계수, 원하는 view와 설정된 광원에 따라 이미지를 만들고 다양한 형태로 출력시킬 수 있는 다양한 기능을 제공한다. 본 논문에서는 VIF 렌더링 라이브러리에 대한 구조와 기능별로 분류된 함수에 대하여 설명하며, 실제로 CAD/CAM 시스템과 통합되어 구상설계에서부터 3차원 설계 모델링에 이르기까지의 제조공정에서 설계검증 툴로써 어떻게 활용되고 있는가에 대하여 기술한다.Abstract Engineers and industrial designers want to produce a realistic-looking images of a 3D model without spending a lot of time and money. Photo-realistic images are so useful from the conceptual design, through its verification, to the machining, that most major CAD venders offer built-in as well as add-on photo-realistic rendering capability to their core CAD software. Since 3D model is consists of a set of NURB surfaces in commercial CAD packages, we need a renderer which handles NURB surface as well as other primitives.A new rendering library called VIF (Visual InterFace) provides two photo-realistic rendering modes: A-buffer and Ray tracing. As an input data it takes NURB surfaces as well as polygonal data and produces images in accordance with the surface parameters, view and lights set by user and outputs image with different formats. This paper describes the overall architecture of VIF and its library functions classified by their functionalities, and discusses how VIF is used as a graphical verification tool in manufacturing processes from the conceptual design to 3D modeling.

• Journal of the Semiconductor & Display Technology
• /
• v.10 no.4
• /
• pp.7-13
• /
• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.21 no.5
• /
• pp.79-89
• /
• 1984

In this paper we present development of microprocessor-based 8-channel statistical multiplexer (SMUX). The hardware design includes one Z-80A CPU board with the clock rate of 4 MHz, one 16 Kbyte ROM board for program storage, one 16 Kbyte dynamic RAM board and three I/O boards, all connected through an S-100 compatible tristate bus. The SMUX can presently multiplex 8 channels with data rates ranging 50 bps to 9600 bps, but can be reduced to accommodate 4 channels by having a slight modification of software and removing one terminal I/O board. The system specifications meet CCITT recommendations X.25 link level, V.24, V.28, X.3 and X.28. Significant features of the SMUX are its capability of handling 4 input codes (ASCII, EBCDIC, Baudot, Transcode), the use of a dynamic buffer management algorithm, a diagnostic facility, and the efficient use of a single CPU for all system operation. Throughout the paper, detailed explanations are given as to how the hardware and software of the SMUX system have been designed efficiently.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2018.10a
• /
• pp.35-38
• /
• 2018

This paper describes a low-power MPPT interface for DC-type energy harvesting sources. The proposed circuit consists of an MPPT controller, a bias generator, and a voltage detector. The MPPT controller consists of an MPG (MPPT Pulse Generator) with a schmitt trigger, a logic gate operating according to energy type (light, heat), and a sample/hold circuit. The bias generator is designed by employing a beta multiplier structure, and the voltage detector is implemented using a bulk-driven comparator and a two-stage buffer. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. The simulation results show that the designed circuit consumes less than 100nA of current at an input voltage of less than 3V and the maximum power efficiency is 99.7%. The chip area of the designed circuit is $1151{\mu}m{\times}940{\mu}m$.

• Journal of the Semiconductor & Display Technology
• /
• v.10 no.3
• /
• pp.1-6
• /
• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.10
• /
• pp.61-66
• /
• 2007

A gain enhancement rail-to-rail buffer amplifier for liquid crystal display (LCD) source driver is proposed. An op-amp with extremely high gain is needed to decrease the offset voltage of the buffer amplifier. Cascoded floating current source and class-AB control block in the op-amp achieve a high voltage gain by reducing the channel length modulation effect in high voltage technologies. HSPICE simulation in $1\;{\mu}V$ 15 V CMOS process demonstrates that voltage gain is increased by 30 dB. The offset voltage is improved from 6.84 mV to $400\;{\mu}V$. Proposed op-amp is fabricated in an LCD source driver IC and overall system offset voltage is decreased by 2 mV.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.49 no.10
• /
• pp.159-168
• /
• 2012

In this paper, a W-band single-chip receiver MMIC for FMCW(Frequency-modulated continuous-wave) radar is presented using $0.15{\mu}m$ GaAs pHEMT technology. The receiver MMIC consists of a 4-stage low noise amplifier(LNA), a down-converting mixer and a 3-stage LO buffer amplifier. The LNA is designed to exhibit a low noise figure and high linearity. A resistive mixer is adopted as a down-converting mixer in order to obtain high linearity and low noise performance at low IF. An additional LO buffer amplifier is also demonstrated to reduce the required LO power of the W-band mixer. The fabricated W-band single-chip receiver MMIC shows an excellent performance such as a conversion gain of 6.2 dB, a noise figure of 5.0 dB and input 1-dB compression point($P_{1dB,in}$) of -12.8 dBm, at the RF frequency of $f_0$ GHz, LO input power of -1 dBm and IF frequency of 100 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.1
• /
• pp.149-155
• /
• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.