• Journal of Korean Society of Industrial and Systems Engineering
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• v.30 no.1
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• pp.33-40
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• 2007

A multi-server queueing system with finite buffer is considered. The input flow is the BMAP (Batch Markovian Arrival Process). The service time has the PH (Phase) type distribution. Customers from the BMAP enter the system according to the discipline of partial admission. Besides ordinary (positive) customers, the Markovian flow (MAP) of negative customers arrives to the system. A negative customer can delete an ordinary customer in service if the state of its PH-service process belongs to some given set. In opposite case the ordinary customer is considered to be protected of the effect of negative customers. The stationary distribution and the main performance measures of the considered queueing system are calculated.

• Convergence Security Journal
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• v.5 no.1
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• pp.45-52
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• 2005

In this paper, the development specification of the optical burst switching system (OBS) for next generation internet services is presented. The development specification includes the number of input/output nodes, the number of wavelengths, buffer capacity, the capacity/queue size of the controller and maximum burst assembly delay. From the performance parameters related to the OBS design, an mathematical model to maximize the throughput and minimize the data loss is presented, and then efficient heuristic algorithm is also presented to analyze the sensitivity of the system parameters.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.291-297
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 128-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array. This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We designed the circuits with goals of the high-speed computations and the simplified structures.

• Journal of the Korean Society of Environmental Restoration Technology
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• v.5 no.4
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• pp.80-88
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• 2002

Comprehensive landscape architectural services provided from schematic design through construction document for this 22,000 square foot, linear, urban rooftop garden situated on top of an in-ground parking garage. The Butterfly Garden serves as a green buffer between a fully renovated historic, seven story condominium building and 15 newly constructed luxury town houses. The park was developed with the cooperation and input from the Washington Butterfly Society during an intensive design charette. The garden will one day soon serve as an ecological amenity to the residents of Alban Towers as well as the surrounding community.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.833-841
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• 1997

In this paper, the hybrid LB-TJW(Leaky Bucket-Triggered Jumping Window) algorithm for multimedia traffic control is proposed and its performance is evaluated and analyzed. Its architecture is composed of the peak bit rate controller and the average bit rate controller. Generally, the cell which violates the peak bit rate is discraded in LBalgorithm, and the average bit rate of JW or TJW algorithm is better than that of LB algorithm. However, the hybrid LB-TJW algorithm passes it though the network if the cell does not violate the peak bit rate. If the cell violates the peak bit rate, the hybrid LB-TJW algorithm passes it to the average bit rate controller which perforithm to monitor the average bit rate of input traffic. The TJW algorithm monitors the cell that violates the average bit rate. If the cell does not violate the average bit rare, the LB-TJW algorithm passes it through the network. As simulation results, the cell loss rate and the buffer size of the LB-TJW algorithm is reduced to half as much as those of LB algortihm.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10b
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• pp.302-307
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• 2007

RFID를 기반으로 유비쿼터스 환경의 응용 서비스를 지원하는 미들웨어는 지속적으로 끊임없이 입력되는 데이터를 정확하게 실시간으로 처리하고 응용 서비스에서 질의하는 결과를 획득해서 전달하여야 한다. 이와 같은 지속적으로 입력되는 대량의 데이터 스트림을 처리하기 위해서 데이터 스트림 관리 시스템(Data Stream Management System: DSMS)을 개발하기 위한 연구가 진행되고 있다. 기존에 연구되는 데이터 스트림에 대한 알고리즘은 대부분 연속 질의 결과들 사이의 평균 오차를 줄이고, 부하 발생 시 데이터의 우선순위에 따라 버리는 것에 초점이 맞추어져 있다. 본 논문에서는 RFID EPC 라는 데이터 특성에 맞추어 다중버퍼를 이용함으로써 고속의 데이터 처리 능력을 얻고, 각 버퍼마다 일정한 규칙을 통해 질의에 있어서도 빠른 대응을 할 수 있는 알고리즘을 제안한다. 본 논문은 현재 DSMS의 관련 연구와 고속 데이터 처리의 필요성을 말하고, 제안하는 알고리즘 설명과 시뮬레이션을 통해 단일버퍼와 다중버퍼일 경우 데이터 처리 속도 성능 평가와 제안한 알고리즘에 맞도록 버퍼가 생성 되는지 테스트하는 것으로 구성된다.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.6
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• pp.1109-1120
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• 2019

In the field of VLBI, If the quality of the connected network between the VLBI station and the correlation center is ensured, the existing inefficiency of repeatedly storing the observation data in each station and the correlation center can be overcome. In other words, the data center can be unified with the correlation center where data analysis is performed, which can improve data processing speed and productivity. In this paper, we design a massive VLBI data system that directly transmits and stores the observation data stream obtained from the VLBI station to the correlation center via the high - speed network KREONET. Based on this system, VLBI test observations confirmed that the observation data was stored perfectly in the recording system of the correlation center without a single packet loss.

• Journal of Korea Multimedia Society
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• v.10 no.11
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• pp.1384-1397
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• 2007

This paper proposes fast storage techniques for hybrid query of data streams. DSMS(Data Stream Management System) have been researched for processing data streams that have busting income. To process hybrid query that retrieve both current incoming data streams and past data streams data streams have to be stored into disk. But due to fast input speed of data stream and memory and disk space limitation, the main research is not about querying to stored data streams but about querying to current incoming data streams. Proposed techniques of this paper use circular buffer for maximizing memory utility and for make non blocking insertion possible. Data in a disk is compressed to maximize the number of data in the disk. Through experiences, proposed technique show that bursting insertion is stored fast.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1085-1094
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• 1994

We propose a traffic flow control scheme of B-NT with temporary cell buffering and selective cell discarding to prevent congestion state of the network nodes in B-ISDN systems to reduce or suppress output cell strams towards T interface. We define the states of the network nodes as normal, pre-congestion, and congestion. In a pre-congestion state, the loss-sensitive traffic is temporarily buffered to slow down the rate of the output traffic streams. In a congestion state, the delay-sensitive traffic is selectively discarded to suppress the output traffic streams as possible in addition to the cell buffering. We model the input cell streams and the states of the network nodes with Interrupted Bernoulli Process and 3-state Markov chain to analyze the performance of the proposed scheme in the B-NT system. The appropriate size of the cell buffer is explored by means of simulation and the influence on the performance of the proposed scheme by the network node state is discussed. As results, more than 2,00 cells of buffer size is needed for the control of medium of lower than the medium, degree of congestion occurrence in the network node while the control of high degree of congestion occurrence is nearly impossible.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.63-70
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• 2013

This paper describes a high PSRR low-dropout(LDO) linear regulator for wide frequency range without output-capacitor. Owing to both of the cascode compensation technique and the current buffer compensation technique in nested Miller compensation loop, the proposed LDO not only maintaines high stability but also achieves high PSRR over wide frequency range with reasonable on-chip capacitances. Since the external capacitor is removed by the proposed compensation techniques, the cost for pad is eliminated. The designed LDO works under the input voltage range from 2.5V to 4.5V and provides up to 10mA load current with the output voltage of 1.8V. The LDO was implemented with 0.18um CMOS technology and the area is 300um X 120 um. The measured power supply rejection ratio(PSRR) is -76dB and -43dB at DC and 1MHz, respectively. The operating current is 25uA.