• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.52-58
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• 2001

This paper describes a TTL-to-CMOS input buffer of an SRAM which dissipates a small operating power dissipation. The input buffer utilizes a transistor structure with latch circuit controlled by a internal activation clock pulse. During the low state of that pulse, input buffer is disabled to eliminate dc current. Otherwise, the input buffer operates normally. Simulation results showed that the power-delay product of the purposed input buffer is reduced by 33.7% per one input.

• Journal of Electrical Engineering and information Science
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• v.3 no.1
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• pp.28-35
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• 1998

In this paper, an NxN input-buffered crosspoint packet switch which selects a Head of the Line, HOL, packet in contention randomly is analyzed with a new approach. The approach is based on both a Markov chain representation of the input buffer and the probability that a HOL packet is successfully served. The probability as a function of N is derived, and it makes it possible to express the average packet delay and the average number of packets in the buffer as a function of N. The contention resolution policy based on the occupancy of the input buffer is also presented and analyzed with this same approach and the relationship between two selection policies is analyzed in terms of the occupancy of the input buffer.

• Proceedings of the KIEE Conference
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• 2003.11b
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• pp.179-182
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• 2003

A simulation on bootstrapping circuit has been performed by modelling a coaxial cable as a transmission line. It is shown that the bootstrapping circuit could be unstable due to the transmission line effect though an ideal amplifier is used. While the conventional bootstrapping circuit does not cancel the input capacitance of the input buffer, a new bootstrapping circuit that cancels input capacitance of the input buffer has been proposed. The proposed bootstrapping circuit consists of the input buffer of which gam is larger than 1 and a feedback resistor to control the loop gain. The proposed bootstrapping circuit has higher input impedance than that of the conventional circuit.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.82.1-82
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• 2001

It is known that existence of irregular transmission time delay is a major bottleneck for application of advanced robot control schemes to internet telerobotic systems. In the internet teleoperation system, the irregular transmission time delay causes a critical problem, which is unstable and inaccurate. This paper suggests a practical internet teleoperation system with streaming buffer system, which consists of a buffer, a buffer manager, and a control timer. The proposed system converts the irregular transmission time delay to constant. So, the system effectively transmits the control input to a remote site to operate a robot stably and accurately. This feature enables short control input interval. That means the entire system has ...

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1246-1264
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• 2000

An input-output buffering switch operates in either of tow different cell loss modes; Backpressure mode and Queueloss mode. In the previous studies, the Backpressrue mode is more effective at low traffic loads, and the Queueloss mode performs better at high traffic. We propose a new operation mode, called Hybrid mode, which adopts the advantages of he Backpressure and the Queueloss mode. Backpressure and Queueloss modes are distinguished from whether a cell loss occurs at the output buffer or not when output buffer overflows, irrespective of input buffer status. In order to simply combine Backpressure and Queueloss mode, the change of input traffic load must be measured. However, in the Hybrid mode, simply both of the input and output buffer overflow and checked out to determine the cell discard. The performance of the Hybrid mode is compared with those of the Backpressure and the Queueloss mode under random and bursty traffic. This paper show that the Hybrid mode always gives the best performance results for most ranges of load values.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.1
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• pp.36-42
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• 1997

This paper proposes a high-speed contention resolution scheme featuring high flexibility to the bursty traffic for an input buffering ATM switching architecture and its hardware strategy. The scheme is based on the threshold on the occupancy of the input buffer. As the proposed scheme utilizes the threshold, it has high flexibility to the fluctuations of the input traffic. The hardware strategy for the proposed policy is provided with the aim of the simple structure that achieves the reduction of the signal path and the power consumption. The performance on the average buffer size of the proposed policy is performed and compared with the conventional schame under the bursty traffic through both the analysis based on the markov hain and the simulation. The relations among the parameters on the proposed policy is analyzed to improve the performance.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.759-760
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• 2006

In this paper, The author designed on high speed VLD(Variable Length Decoder) using shift buffer. Variable Length Decoder is received N bit data from input block and decode the input signal using Shifting Buffer, Length Decoder and Symbol Decoder blocks. The inner part of shifting buffer in proposed Variable Length Decoder is filled input data and then operating therefore, the proposed structure can improve the decoded speed. And in this paper we applying pipeline structure therefore data is decoded in every clock.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1996.04a
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• pp.314-314
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• 1996

We investigate the scheduling problem for periodic job shops with blocking. We develop Petri net models for periodic job shops with finite buffers. A buffer control method would allow the jobs to enter the input buffer of the next machine in the order for which they are completed. We discuss difficulties in using such a random order buffer control method and random access buffers. We thus propose an alternative buffer control policy that restricts the jobs to enter the input buffer of the next machine in a predetermined order. The buffer control method simplifies job flows and control systems. Further, it requires only a cost-effective simple sequential buffer. We show that the periodic scheduling model with finite buffers using the buffer control policy can be transformed into an equivalent periodic scheduling model with no buffer, which is modeled as a timed marked graph. We characterize the structural properties for deadlock detection. Finally, we develop a mixed integer programming model for the no buffer problem that finds a deadlock-free optimal sequence that minimizes the cycle time.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.181-184
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• 2000

In this paper, we described a design of the input buffer system for efficiently dealing with MPEG audio bitstream to demux header and side information, audio data. In order to overcome the limitations of fixed-word manipulation in bitstream demuxing, we proposed a new variable length bit retrieval system with FSM sequencer supporting MPEG audio frame format, and serial buffer demuxing audio stream, FIFO circular buffer including header and side information.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.283-286
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• 2000

One major drawback of conventional output buffered switches is that the speed of writing cells into output buffer should be N times faster than input link speed. This paper proposes a new output buffer switch that divides one output buffer into several buffers and virtually shares the divided buffers by using a distributor. The proposed switch makes it possible to reduce the memory speed. The proposed switch is evaluated in terms of the average cell latency compared with the input buffered switches which use the arbitration alogorithms, i.e., iSLIP or wrapped wave front arbiter(WWFA).