• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.3
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• pp.15-26
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• 2008

This paper proposes a new sinusoidal rectifier which improves input factor and input current waveform without complicated switching modulation such as pulse width or a complicated feed back control. The proposed rectifier consists of a pair of capacitors connected in series, a full bridge diode rectifier, a pair of inductors, and a pair of switching devices connected in series. While the configuration of the sinusoidal rectifier is simple in itself, it effectively reduces the reactive power and harmonics involved(IEC555-2 SC77A90 Class C) in input line current. The excellent properties of the new sinusoidal rectifier are verified by theoretical analysis and experimental results.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.19-21
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• 2007

This paper proposes an input waveform improvement using VIENNA Rectifier(three-phase/level/switch). VIENNA Rectifier is based on the combination of a three-phase diode bridge and dc/dc converter. It features low input current ripple and sinusoidal mains current form.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.556-560
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• 2001

In this paper, a soft-switching discontinuous mode (DCM) power factor corrected (PFC) converter is analyzed by applying the double Fourier series expansion. It is found that the fundamental component and higher-order harmonics included in the input current waveform are obtained by the Fourier series expansion of the mean value of the inductor current. From the theoretical analysis, a new method removing the distortion of the input current waveform is proposed. In spite of an open loop system, the proposed method makes a great improvement of the total harmonic distortion even if the ratio of output voltage to input voltage is very low.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.17 no.1
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• pp.116-123
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• 2003

In this paper, interleaved boost converter is applied as a pre-regulator in switched mode power supply. The pre-regulator plays a role to improve power factor. Interleaved Boost Power Factor Corrector(IBPFC) can reduce input current ripple as a single voltage control loop only without inner current loop, because input current is divided each 50% by two switching devices. Each converter cell is also operated in discontinuous current mode and inductor current of each converter is discontinuous. Total input current which is composed by each converter cell is continuous current. Thus, IBPFC is able to improve input current ripple. IBPFC operating in discontinuous current mode can be classified as six modes from switching state and be carried out state space averaging small signal modeling. A control transfer function is obtained according to the modeling. Single voltage control loop is also constructed by the control transfer function. From experimental result, improvement of power factor and input current ripple are verified.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.7
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• pp.343-351
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• 2003

In this paper, interleaved boost converter is applied as a first-stage converter in switch mode power supply. The first-stage converter plays a role to improve power factor. Interleaved Boost Power Factor Corrector(IBPFC) can reduce input current ripple as a single voltage control loop only without inner current loop, because input current is divided each 50% by two switching devices. Each converter cell is also operated in discontinuous current mode and inductor current of each converter is discontinuous. Total input current which is composed by each converter cell is continuous current. Thus, IBPFC is able to improve input current ripple. IBPFC operating in discontinuous current mode can be classified as six modes from switching state and be carried out state space averaging small signal modeling. A control transfer function is obtained according to the modeling. Not only steady-state characteristics but also dynamic characteristics is considered. Single voltage control loop is also constructed by the control transfer function. From experimental result, improvement of power factor and input current ripple are verified.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.2
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• pp.363-368
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• 2009

In the paper, we confirmed improvement Noise figure of the entire RF front-end using spiral inductor with PGS(Patterned Ground Shield) and current bleeding techniques. LNA design is to achieve simultaneous noise and input matching. Spiral inductor in input circuit of LNA inserted PGS for betterment of Q-factor. we modeling inductor using EM simulator, so compared with inductor of TSMC 0.18um. We designed and simulation the optimum structure of PGS using Taguchi's method. We confirmed enhancement of noise figure at LNA after substituted for inductor with PGS. Mixer designed using current bleeding techniques for reduced noise. We designed LNA using inductor with PGS and Mixer using current bleeding techniques, so confirmed improvement of noise figure.

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.432-435
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• 1997

This Paper proposes a novel sinusoidal converter which improves input power factor and input current waveform without any complicated switching modulation such as a pulse width modulation or a complicated feed-back control. It is composed of a full bridge diode, a pair of capacitors, a pair of inductors and a pair of switching devices. The configuration and control strategy are both simple however, the sinusoidal converter effectively reduces reactive power and hamonics included in a input line current. Excellent behavior of the proposed converter is verified by theoretical analysis and experimental results.

• Proceedings of the KWS Conference
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• 2002.10a
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• pp.107-112
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• 2002

Ferritic stainless steels would be the most important alloys under the chloride environment. They are a cheaper alternative to austenitic stainless steels [1]. The present study is related to gas tungsten arc welding (GTAW) characteristics of Type 444 stainless steels. The heat of welding leads to grain coarsening in the HAZ and in the weld metal of ferritic stainless steels because they solidify directly from the liquid to the ferritc phase without any intermediate phase transformation. It is therefore recommended that these alloys be welded with a low heat input and at high welding speeds. Attempts to improve weldability were made by using of direct current straight polarity (DCSP) and pulsed current GTAW processes in this study. Measuring weld bead, grain size and Erichsen test were performed and the effects of heat input, pulse frequency on the weld metal and HAZ were studied. The main results were obtained as followings: decreasing heat input was effective to control the width of weld both in DCSP welding and in pulsed current welding; pulsed current welding was found to refine the grain size effectively and the finest grain size was found at the frequency of 150Hz in pulsed current welding; it was found that decreasing heat input also refine the HAZs effectively and the frequency had no different effect on HAZ at the same heat input; the ductility could be improved effectively in pulsed current welding.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.79-85
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• 2008

It is important to consider the life of battery and low power operation for various wireless communications. Thus, Analog current-mode signal processing with SI circuit has been taken notice of in designing the LSI for wireless communications. However, in current mode signal processsing, current memory circuit has a problem called clock-feedthrough. In this paper, we examine the connection of CMOS switch that is the common solution of clock-feedthrough and calculate the relation of width between CMOS switch for design methodology for improvement of current memory. As a result of simulation, when the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the width relation in CMOS switch is obtained with $W_{Mp}=5.62W_{Mn}+1.6$, for the nMOS width of 2~6um in CMOS switch. And from the same simulation condition, it is obtained with $W_{Mp}=2.05W_{Mn}+23$ for the nMOS width of 6~10um in CMOS switch. Then the defined width relation of MOS transistor will be useful guidance in design for improvement of current memory.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.4
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• pp.302-305
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• 2021

Selection of the optimal inductance for power factor improvement of a buck AC/DC light-emitting diode (LED) driver with wide input voltage range is described in this study. The power factor change based on the slope compensation is obtained for various normalized output current (NOC) values using discrete-time domain analysis. The possibility of implementing constant slope compensation is described using power factor curves for various NOC values. NOC = 0.5 is chosen for the value of inductance with consideration for the simple implementation and reduction of inductor size. Experimental results of the inductance corresponding to NOC = 0.5 are presented.