• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.114-121
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• 2000

The problem of an input-buffered switch is the HOL(head-of-line) blocking which limits the maximum throughput but it is easy to implement in hardware. However, HOL blocking can be eliminated using aVOQ(virtual-output-queueing) technique. 0 this paper, we propose a new cell-scheduling algorithm for aninput-buffered ATM switch. The proposed algorithm, called PPIM(Probabilistic Parallel Iterative Matching), imposesa weight to every request based on the reserved bandwidth. It is shown that the input-buffered ATM switch withthe proposed PPIM algorithm not only provides high throughput and low delay but it also reduces the jitter,compared with the existing WPIM(Weighted PIM).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.142-145
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• 1999

In this paper, delay performances are evaluated and compared for three dual-plane switch architectures; dual input queue/dual switching plane (DQDP The terms of DQDP, DQDP-PS and DQDP-GQ were not used in [Turner88], [Lee96] and [Son97]. All these tern are designated in this letter for convenience.) switch, DQDP with plane selector (DQDP-PS) switch and DQDP based on output group queueing (DQDP-OGQ) switch. We show that under random traffic these switches give almost identical delay performances to that of the output queueing switch but under bursty traffic only the DQDP-PS and the DQDP-OGQ switches ran do.

• Journal of Korean Institute of Industrial Engineers
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• v.25 no.2
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• pp.233-239
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• 1999

With the increase of Internet protocol (IP) packets the performance of routers became an important issue in internetworking. In this paper we examined the matching algorithm in gigabit router which has input queue with virtual output queueing. Port partitioning concept is employed to reduce the computational burden of the scheduler within a switch. The input and output ports are divided into two groups such that the matching algorithm is implemented within each input-output pair group in parallel. The matching is performed by exchanging input and output port groups at every time slot to handle all incoming traffics. Two algorithms, maximal weight matching by port partitioning (MPP) and modified maximal weight matching by port partitioning (MMPP) are presented. MMPP has the lowest delay for every packet arrival rate. The buffer size on a port is approximately 20-60 packets depending on the packet arrival rates. The throughput is illustrated to be linear to the packet arrival rate, which can be achieved under highly efficient matching algorithm.

• Journal of Internet Computing and Services
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• v.9 no.2
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• pp.15-23
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• 2008

This paper proposes the new structural MOQ(Multiple Input/Output-Queued) switch which guarantees QoS while maintaining high efficiency and deals with the Anti-Empty algorithm which is new arbitration algorithm to be used for the proposed switch. The new structure of the proposed switch based on MIQ, MOQ is designed to have the same buffer speed as the external line speed. Also, the proposed switch makes it possible to remove the weak point of existing methods and introduces the new method of the MOQ operation to support QoS. Therefore, this switch is equal to the Output Queued switch in efficiency and delay, and guarantees the high-speed switching supporting QoS without cell loss.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.6
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• pp.365-371
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• 2003

Input queued switch is useful for high bandwidth switches and routers because of lower complexity and fewer circuits than output queued. The input queued switch, however, suffers the HOL-Blocking, which limits its throughput to 58%. To overcome HOL-Blocking problem, many input-queued switch controlled by a scheduling algorithm. Most scheduling algorithms are implemented based on a centralized scheduler which restrict the design of the switch architecture. In this paper, we propose a simple scheduler called Pipelined Round Robin (PRR) which is intrinsically distributed by each input port. We presents to show the effectiveness of the proposed scheduler.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.3
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• pp.179-196
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• 1986

In this paper, the peformance of a statistical packet voice/data multiplexer is studied. In ths study we assume that in the packet voice/data multiplexer two separate finite queues are used for voice and data traffics, and that voice traffic gets priority over data. For the performance analysis we divide the output link of the multiplexer into a sequence of time slots. The voice signal is modeled as an (M+1) - state Markov process, M being the packet generation period in slots. As for the data traffic, it is modeled by a simple Poisson process. In our discrete time domain analysis, the queueing behavior of voice traffic is little affected by the data traffic since voice signal has priority over data. Therefore, we first analyze the queueing behavior of voice traffic, and then using the result, we study the queueing behavior of data traffic. For the packet voice multiplexer, both inpur state and voice buffer occupancy are formulated by a two-dimensional Markov chain. For the integrated voice/data multiplexer we use a three-dimensional Markov chain that represents the input voice state and the buffer occupancies of voice and data. With these models, the numerical results for the performance have been obtained by the Gauss-Seidel iteration method. The analytical results have been verified by computer simylation. From the results we have found that there exist tradeoffs among the number of voice users, output link capacity, voic queue size and overflow probability for the voice traffic, and also exist tradeoffs among traffic load, data queue size and oveflow probability for the data traffic. Also, there exists a tradeoff between the performance of voice and data traffics for given inpur traffics and link capacity. In addition, it has been found that the average queueing delay of data traffic is longer than the maximum buffer size, when the gain of time assignment speech interpolation(TASI) is more than two and the number of voice users is small.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.4
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• pp.329-333
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• 2003

In this paper we analyze the performance of the low latency pre-registration handoff method of mobile IP by computer simulation. Packet losses and delays are evaluated in terms of system utilization. Foreign agents that participate in the handoff process can be modeled as queues representing input and output ports. Therefore, we propose an analytical model of pre-registration handoff by using open queueing network model. Simulation results are shown for validating analytical estimates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1289-1295
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• 1999

본 논문에서는 스위치의 운용 알고리즘에 따라 시뮬레이션 프로그램을 이용하여 입/출력 버퍼의 셀 손실율을 측정하였다. 그 결과 셀 손실에 영향을 주는 요소로서, 셀 도착 간격 시간(k(a))과 SPEEDUP FACTOR(SF) en 가지 요소에 따라 셀손실을 평가할 수 있음을 알 수 있었다. 셀 도착 간격 시간 혹은 주기성은 비트가 셀로 모이는데 걸리는 시간을 의미하며 스위치 속도 SF는 임의의 한 슬롯내에서 한 입력단에서 출력단으로 서비스 가능한 셀의 수를 나타내고 있다. 시뮬레이션의 결과에서 보면 입력 버퍼에서는 주지성에 따라, 출력 버퍼에서는 SF의 크기에 따라 셀손실율이 커진다는 사실을 알 수 있었다. 따라서 보다 정확한 고속 스위칭 향상을 위해서는 입/출력 버퍼의 크기 결정이 중요하다. 본 논문의 시뮬레이션 결과에서는 입력 버퍼가 100x셀 일 때 출력 버퍼가 40x셀 정도의 크기가 적합하다는 것을 얻어내었다. 물론 입/출력 버퍼를 크게 한다면 셀 손실이 작아지지만, 하드웨어를 구성하는데 문제점이 발생될 것이기 때문이다. 그리고 본 논문 결과치중 셀 도착 분포 상황은 변동계수 모델링 성정에 따라 SF가 처리하는 서비스의 셀 도착 분포에 의 \ulcorner달라지지만, 변동계수가 전혀 없는 이상적인 경우(CV=1)를 제외한 경우의 SF값을 만족한다고 하겠다. 끝으로 입/출력 버퍼를 가진 스위치 구조는 단지 출력 버퍼를 갖는 스위치 보다 지연이 크지만, VLSI의 발달로 셀의 처리 속도가 증가하므로 더 많은 장점을 갖게 될 것이다.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.45 no.4
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• pp.53-60
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• 2022

In a group-testing method, instead of testing a sample, for example, blood individually, a batch of samples are pooled and tested simultaneously. If the pooled test is positive (or defective), each sample is tested individually. However, if negative (or good), the test is terminated at one pooled test because all samples in the batch are negative. This paper considers a queueing system with a two-stage group-testing policy. Samples arrive at the system according to a Poisson process. The system has a single server which starts a two-stage group test in a batch whenever the number of samples in the system reaches exactly a predetermined size. In the first stage, samples are pooled and tested simultaneously. If the pooled test is negative, the test is terminated. However, if positive, the samples are divided into two equally sized subgroups and each subgroup is applied to a group test in the second stage, respectively. The server performs pooled tests and individual tests sequentially. The testing time of a sample and a batch follow general distributions, respectively. In this paper, we derive the steady-state probability generating function of the system size at an arbitrary time, applying a bulk queuing model. In addition, we present queuing performance metrics such as the offered load, output rate, allowable input rate, and mean waiting time. In numerical examples with various prevalence rates, we show that the second-stage group-testing system can be more efficient than a one-stage group-testing system or an individual-testing system in terms of the allowable input rates and the waiting time. The two-stage group-testing system considered in this paper is very simple, so it is expected to be applicable in the field of COVID-19.

• Management Science and Financial Engineering
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• v.4 no.2
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• pp.43-58
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• 1998

Packet switch is a key component in high speed digital networks. This paper investigates congestion phenomena in the packet switching with input buffers. For large value of switch size N, mathematical models have been developed to analyze asymptotic maximum switch throughput under nonuniform traffic. Simulation study has also been done for small values of finite N. The rapid convergence of the switch performance with finite switch size to asymptotic solutions implies that asymptotic analytical solutions approximate very closely to maximum throughputs for reasonably large but finite N. Numerical examples show that non-uniformity in traffic pattern could result in serious degradation in packet switch performance, while the maximum switch throughput is 0.586 when the traffic load is uniform over the output trunks. Window scheduling policy seems to work only when the traffic is relatively uniformly distributed. As traffic non-uniformity increases, the effect of window size on throughput is getting mediocre.