• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.117-120
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• 1999

Input queueing is useful for high bandwidth switches and routers because of lower complexity and fewer circuits than output queueing. The input queueing switch, however, suffers HOL-Blocking, which limits the throughput to 58%. To get around this low throughput, we propose a simple scheduling algorithm called Synchronous Input Port (SIP). This method synchronize packets and switching without blocking, which is shown to have better performance over the established algorithms

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.2
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• pp.1-9
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• 1998

ATM was adopted as the switching and multiplexing technique for BISDN which aims at transmitting traffics with various characteristics in a unified network. To construct these ATM networks, the most important aspect is the design of the switching system with high performance and different service capabilities. In this paepr, we analyze the performance of an input and output queueing switch with preemptive priority which is considered to be most suitable for ATM networks. For the analysis of an input queue, we model each input queue as two separate virtual input queues for each priority class and we approximage them asindependent Geom/Geom/1 queues. And we model a virtual HOL queue which consists of HOL cells of all virtual input queues which have the same output address to obtain the mean service time at each virtual input queue. For the analysis of an output quque, we obtain approximately the arrival process into the output queue from the state of the virtual HOL queue. We use a Markov chain method to analyze these two models and obtain the maximum throughput of the switch and the mean queueing delay of cells. and analysis results are compared with simulation to verify that out model yields accurate results.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.12
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• pp.58-66
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• 2001

Input queueing is useful for high bandwidth switches and routers because of lower complexity and fewer circuits than output queueing. The input queueing switch, however, suffers HOL-Blocking, which limits the throughput to 58%. To get around this low throughput, many input queueing switches have centralized scheduler, which centralized scheduler restrict the design of the switch architecture. To overcome this problem, we propose a simple scheduler called PRR(Pipelined Round Robin), which is intrinsically distributed and presents to show the effectiveness of the proposed scheduling.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1148-1159
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• 1997

In the broadband integrated service digital networks (B-ISDN), ATM switches hould be abld to accommodate diverse types of applications ith different traffic characteristics and quality ddo services (QOS). Thus, in order to increase the utilization of switches and satisfy the QOS's of each traffic type, some types of priority control schemes are needed in ATM switches. In this paper, a nonblocking input and output queueing ATm switch with capacity C is considered in which two classes of traffics with different loss probability constraints are admitted. 'Partial push-out' algorithm is suggested as a loss priority control schemes, and the performance of this algorithm is analyzed when this is adopted in input buffers of the switch. The quque length distribution of input buffers and loss probabilities of each traffic are obtained using a matrix-geometric solution method. Numerical analysis and simulation indicate that the utilization of the switch with partial push-out algorithm satisfying the QOS's of each traffic is much higher than that of the switch without control. Also, the required buffer size is reduced while satisfying the same QOS's.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.812-822
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• 1997

In this paper, we propose an architecture of the asynchronous shared-bus type switch with priority and fairness schemes. The switch architecture is an input and output queueing system, and the priority scheme is implemented in both input and output queues. We analyze packet delay of both input and output queues. In the analysis, we consider to stations with asymmetric arrival rates. Although we make some approximations in the analysis, the numerical results show good agreements with the simulation results.

• Journal of KIISE:Information Networking
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• v.29 no.5
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• pp.553-561
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• 2002

We present a novel service discipline, called linear service discipline, to serve multiple QoS queues sharing a resource and analyze its properties. The linear server makes the output traffic and the queueing dynamics of individual queues as a linear function of its input traffic. In particular, if input traffic is Gaussian, the distributions of queue length and output traffic are also Gaussian with their mean and variance being a function of input mean and input power spectrum (equivalently, autocorrelation function of input). Important QoS measures including buffer overflow probability and queueing delay distribution are also expressed as a function of input mean and input power spectrum. This study explores a new direction for network-wide traffic management based on linear system theories by letting us view the queueing process at each node as a linear filter.

• Journal of Internet Computing and Services
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• v.8 no.5
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• pp.161-170
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• 2007

The proposed switch which has separated data plane and switching plane can make parallel processing for packet data storing, memory address pointer switching and simultaneously can be capable of switching the variable length for IP packets. The proposed architecture does not require the complicated arbitration algorithms in VOQ, also is designed for QoS of generic output queue switch as well as input queue. At the result of simulations, the proposed architecture has less average packet delay than the one of the memory-sharing based architecture and guarantees keeping a certain average packet delay in increasing switch size.

• Journal of Korean Institute of Industrial Engineers
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• v.17 no.2
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• pp.107-113
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• 1991

This article develops a control model for an open queueing network in terms of both the input and the output processes with stochastic intensities. The input and the output intensities are subject to some capacity limits and optimum control is characterized by a threshold type with a finite upper barrier. A discounted profit is used as a decision criteria, which is revenue minus operating and holding cost.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1184-1195
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• 1998

In this paper, we compare vaious input-buffered ATM switch architectures in structures on input buffer and switching fabric, the resons for performance improvement and degradation, arbitration scheme and maximum throughput, and present comparative merits and demerits of each architecture under random and bursty traffic. We also analyze the prformance of combined architectures of windowing scheme, destination-queueing based input-port expansion schemeand output-port expansion scheme, and show that it is possible to achieve 100% throughput with combined scheme of destination-queueing based input-port expansion scheme and output-port expansio scheme when the number of output group is 2 and output port expansion ratio is 2.

• Journal of Korean Institute of Industrial Engineers
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• v.21 no.2
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• pp.167-181
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• 1995

We develop an analytical model to estimate the time a workpiece spends in both input and output queues in trip-based material handling systems. The waiting times in the input queues are approximated by M/G/1 queueing system and the waiting times in the output queues are estimated using the method discussed in Bozer, Cho, and Srinivasan [2]. The analytical results are tested via simulation experiment. The result indicates that the analytical model estimates the expected waiting times in both the input and output queues fairly accurately. Furthermore, we observe that a workpiece spends more time waiting for a processor than waiting for a device even if the processors and the devices are equally utilized. It is also noted that the expected waiting time in the output queue with fewer faster devices is shorter than that obtained with multiple slower devices.