• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.3
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• pp.1131-1143
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• 2016

Differential detection schemes do not require any channel estimation, which can be employed under user mobility with low computational complexity. In this work, a soft-input soft-output (SISO) differential detection algorithm is proposed for amplify-and-forward (AF) over time-varying relaying channels based cooperative communications system. Furthermore, maximum-likelihood (ML) detector for M-ary differential Phase-shift keying (DPSK) is derived to calculate a posteriori probabilities (APP) of information bits. In addition, when the SISO is exploited in conjunction with channel decoding, iterative detection and decoding approach by exchanging extrinsic information with outer code is obtained. Finally, simulation results show that the proposed non-coherent approach improves detection performance significantly. In particular, the system can obtain greater performance gain under fast-fading channels.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.76-90
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• 1994

In this paper, an efficient algorithm is proposed which recognizes the mixed document consisting of the printed Korean/alphanumeric texts and graphic images. In the preprocessing step an input document is aligned if necessary by rotating it. We obtain the rotation angle using the Hough transform and align the input document horizontally. Then we separate graphic image parts from text parts by considering chain codes of connected components. We further separate each character using vertical and horizontal projections. In the recognition step Korean and alphanumeric characters are classified and each of them is recognized hierarchically using several features. In summary an efficient recognition algorithm for mixed documents is proposed and its performance is demonstrated via computer simulations.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.2
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• pp.159-167
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• 1996

In this paper, a new competitive learning algorithm called dynamic competitive learning (DCL) is presented. DCL is a supervised learning mehtod that dynamically generates output neuraons and nitializes weight vectors from training patterns. It introduces a new parameter called LOG (limit of garde) to decide whether or not an output neuron is created. In other words, if there exist some neurons in the province of LOG that classify the input vector correctly, then DCL adjusts the weight vector for the neuraon which has the minimum grade. Otherwise, it produces a new output neuron using the given input vector. It is largely learning is not limited only to the winner and the output neurons are dynamically generated int he trining process. In addition, the proposed algorithm has a small number of parameters. Which are easy to be determined and applied to the real problems. Experimental results for patterns recognition of remote sensing data and handwritten numeral data indicate the superiority of dCL in comparison to the conventional competitive learning methods.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.1
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.

• Journal of Institute of Control, Robotics and Systems
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• v.1 no.2
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• pp.105-111
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• 1995

This paper proposes a segmentation algorithm using gray-level discontinuity and surface reflectance ratio of input images obtained under different illumination conditions. Each image is divided by a certain number of subregions based on the thresholds. The thresholds are determined using the histogram of fusion image which is obtained by ANDing the multiple input images. The subregions of images are projected on the eigenspace where their bases are the major eigenvectors of image matrix. Points in the eigenspace are classified into two clusters. Images associated with the bigger cluster are fused by revised ANDing to form a combined edge image. Missing edges are detected using surface reflectance ration and chain code. The proposed algorithm obtains more accurate edge information and allows to more efficiently recognize the environment under various illumination conditions.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.121-124
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• 2001

This paper proposed resource allocation algorithm for the minimum switching activity of functional unit in high level synthesis process as like DSP which is circuit to give many functional unit. The resource allocation method after scheduling use the power function calculating average hamming distance and switching activity of the between two input. First of all, the switching activity is calculated by the input value after calculating the average hamming distance between operation. In this paper, the proposed method though high If level simulation find switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity find the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and max control step. And it is the reduction effect from 6% to 8%.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.55-63
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• 1998

This paper presents a new maching algorithm by Hopfield Neural Network for 3-D object recognition. In the proposed method, a model object is represented by a set of polygons in a single coordinate. And each polygon is described by a set of features; feature attributes. In case of 3-D object recognition, the scale and poses of the object are important factors. So we propose a strategy for 3-D object recognition independently to its scale and poses. In this strategy, the respective features of the input or the model objects are changed to the startegical constants when they are compared with one another. Finally, we show that the proposed method has a robustness through the results of experiments which included the classification of the input objects and the matching sequence to its 3-D rotation and scale.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.7
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• pp.1003-1009
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• 1995

In This Paper, Linearization problem is discussed to reduce distortion of a nonlinear system based on Schetzen's pth-orfer inverse theorem. We propose a nonlinear adaptive prefiltering algorithm which can reduse nonlinear distortion up to pth order by tandemly connecting a pth-order Volterra filter before the nonlinear system under the consideration and by adjusting the filter coefficients adaptively. The feasibility of applying the proposed algorithm to a nonlinear system is conformed via computer simulation by observing significant reduction of total nonlinear distortion for the case of random input and sinusoidal input excitation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.7
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• pp.55-62
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• 1994

Interpattern association (IPA) model which the interconnection weight matrix(IWM) is constructed by the association between patterns is effective in similar pattern recognitions. But, if the number of reference patterns is increased, the ability of recognition is decreased. Using a hierarchical recognition algorithm which adopts the tree search strategy, we classified reference patterns into sub-groups by similarity. In IPA model, if input includes random noise we make it converge to reference pattern by means of input includes random noise we make it converge to reference pattern by means of increasing the number of pixels of prohibited state in IWM. In relation to reference patterns the pixel of prohibited state made partially prohibited state of no connected state using which is not included common and feature regions by each reference patterns.