• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.41 no.6
• /
• pp.19-24
• /
• 2004

A novel fast parallel NTGST is proposed for high resolution computer vision inspection of the BLUs in a LCD production line. The conventional computation- intensive NTGST algorithm is modified and its C codes are optimized into fast NTGST to be adapted to the SIMD parallel architecture. And then, the input inspection image is partitioned and allocated to each of the P processors in multi-threaded implementation, and the NTGST is executed on SIMD architecture of N data items simultaneously in each thread. Thus, the proposed inspection system can achieve the speedup of O(NP). Experiments using Dual-Pentium III processor with its MMX and extended MMX SIMD technology show that the proposed parallel NTGST is about Sp=8 times faster than the conventional NTGST, which shows the scalability of the proposed system implementation for the fast, high resolution computer vision inspection of the various sized BLUs in LCD production lines.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.41 no.4
• /
• pp.85-94
• /
• 2004

Object tracking in a real time image is one of interesting subjects in computer vision and many Practical application fields during the past couple of years. But sometimes existing systems cannot find all objects by recognizing background noise as object. This paper proposes a method of object detection and tracking using adaptive background image in real time. To detect object which is not influenced by illumination and to remove noise in background image, this system generates adaptive background image by real time background image updating. This system detects object using the difference between background image and input image from camera. After setting up Minimum Bounding Rectangle(MBR) using the internal point of detected object, the system tracks object through this MBR In addition, this paper evaluates the test result about performance of proposed method as compared with existing tracking algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.5
• /
• pp.65-73
• /
• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.12
• /
• pp.59-68
• /
• 1999

The timing characteristics of an ASIC are analyzed based on the propagation delays of each gate and interconnect wire. The gate delay can be modeled using the two-dimensional delay table whose index variables are the input transition time and the output load capacitance. The AWE technique can be adopted as an algorithm to compute the interconnect delay. Since these delays are affected by the interaction to the two-dimensional delay table and the AWE technique. A method to model this effect has been proposed through the effective capacitance and the gate driver model under the assumption of single driving gate. This paper presents a new technique to handle the multiple CMOS gates driving interconnect wire by extending previous approach. This technique has been implemented in C language and applied to several interconnect circuits driven by multiple CMOS gates. In most cases, we found a few tens of speed-up and only a few percents of errors in computing both of gate and interconnect delays, compared to SPICE.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.12
• /
• pp.66-72
• /
• 2009

This paper proposes an efficient binary arithmetic encoder for CABAC which is used one of the entropy coding methods for H.264/AVC. The present binary arithmetic encoding algorithm requires huge complexity of operation and data dependency of each step, which is difficult to be operated in fast. Therefore, renormalization exploits 2-stage pipeline architecture for efficient process of operation, which reduces huge complexity of operation and data dependency. Context model updater is implemented by using a simple expression instead of transIdxMPS table and merging transIdxLPS and rangeTabLPS tables, which decreases hardware size. Arithmetic calculator consists of regular mode, bypass mode and termination mode for appearance probability of binary value. It can operate in maximum speed. The proposed binary arithmetic encoder has 7282 gate counts in 0.18um standard cell library. And input symbol per cycle is about 1.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.36S no.12
• /
• pp.107-119
• /
• 1999

There is no authentic solution in a face detection problem though it is an important part of pattern recognition and has many diverse application fields. The reason is that there are many unpredictable deformations due to facial expressions, view point, rotation, scale, gender, age, etc. To overcome these problems, we propose an algorithm based on feature-based method, which is well known to be robust to these deformations. We detect a face by calculating a similarity between the formation of real face feature and candidate feature formation which consists of eyebrow, eye, nose, and mouth. In this paper, we use a steerable filter instead of general derivative edge detector in order to get more accurate feature components. We applied deformable template to verify the detected face, which overcome the weak point of feature-based method. Considering the low detection rate because of face detection method using whole input images, we design an adaptive skin-color filter which can be applicable to a diverse skin color, minimizing target area and processing time.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.38 no.2
• /
• pp.1-11
• /
• 2001

In this paper, a chattering alleviation VSS controller for the sinusoidal type BLDC motor is designed. Dead Zone function is proposed to change the chattering occurring in the transient state from high frequency to low frequency and time varying gains arc applied for the control input to eliminate the steady state excessive chattering in the conventional ISM. The proposed Dead Zone function represents the sliding layer composed of two switching surfaces and if a state vector exists in this layer, the chattering don't occur. Simulation and experimental results confirm the useful effects of the above algorithm.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.6
• /
• pp.712-716
• /
• 2010

In this paper, we propose a novel shape-based approach to detect CNV regions (CNVR) by analyzing the coverage graph obtained by aligning the giga-sequencing data onto the human reference sequence. The proposed algorithm proceeds in two steps: a filtering step and a post-processing step. In the filtering step, it takes several shape parameters as input and extracts candidate CNVRs having various depth and width. In the post-processing step, it revises the candidate regions to make up for errors potentially included in the reference sequence and giga-sequencing data, and filters out regions with high ratio of GC-contents, and returns the final result set from those candidate CNVRs. To verify the superiority of our approach, we performed extensive experiments using giga-sequencing data publicly opened by "1000 genome project" and verified the accuracy by comparing our results with those registered in DGV database. The result revealed that our approach successfully finds the CNVR having various shapes (gains or losses) in HLA (Human Leukocyte Antigen) region.

• Journal of KIISE
• /
• v.45 no.1
• /
• pp.22-29
• /
• 2018

Over the decades, neural networks have been successfully used in numerous applications from speech recognition to image classification. However, these neural networks cannot explain their results and one needs to know how and why a specific conclusion was drawn. Most studies focus on extracting binary rules from neural networks, which is often impractical to do, since data sets used for machine learning applications contain continuous values. To fill the gap, this paper presents an algorithm to extract logic rules from a trained neural network for data with continuous attributes. It uses hyperplane-based linear classifiers to extract rules with numeric values from trained weights between input and hidden layers and then combines these classifiers with binary rules learned from hidden and output layers to form non-linear classification rules. Experiments with different datasets show that the proposed approach can accurately extract logical rules for data with nonlinear continuous attributes.

• Journal of KIISE
• /
• v.44 no.11
• /
• pp.1209-1218
• /
• 2017

A variety of sensors is widely used these days, and it has become much easier to acquire spatial big data streams from various sources. Since spatial data streams have inherently skewed and dynamically changing distributions, the system must effectively distribute the load among workers. Previous studies to solve this load imbalance problem are not directly applicable to processing spatial data. In this research, we propose Adaptive Spatial Key Grouping (ASKG). The main idea of ASKG is, by utilizing the previous distribution of the data streams, to adaptively suggest a new grouping scheme that evenly distributes the future load among workers. We evaluate the validity of the proposed algorithm in various environments, by conducting an experiment with real datasets while varying the number of workers, input rate, and processing overhead. Compared to two other alternative algorithms, ASKG improves the system performance in terms of load imbalance, throughput, and latency.