• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.9
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• pp.42-50
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• 2015

The Buck-Boost converter consisted of two switches is more expensive than the conventional Buck converter, because of the increase of the components. However, it can control the DC voltage depending on the requested load voltage without additional circuits, because it can control the voltage under the relatively wide range of the load. Additionally, it can control the output voltage constantly under the variation of the input voltage. In the paper two control loops consisted of current and voltage control are designed. When two controllers are operated at the same time the problem of the output voltage is occurred. Therefore, the solution of the output voltage problem is proposed. Finally, the validity of the proposed scheme is investigated with simulated and experimental results for a prototype system rated at 1kVA.

• Journal of Power Electronics
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• v.12 no.4
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• pp.587-594
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• 2012

When a PWM rectifier has a low DC-link voltage during startup, the output voltage vector cannot be high enough to regulate the input current. This lack of a PWM rectifier output voltage vector can cause an unregulated inrush current when the rectifier operation starts. This paper presents a PWM rectifier start-up current control algorithm for when it starts operation with a lower DC-link voltage than unloaded condition case. To avoid the unregulated inrush current caused by a lack of DC-link voltage, the proposed control scheme regulates the one phase current with one switch chopping and it generates the current command considering the uncontrolled current magnitude information, which is calculated in advance. Simulation and experiment results support the validity of the proposed method.

• ETRI Journal
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• v.34 no.1
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• pp.110-113
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• 2012

We propose a very-low-complexity lattice-reduction (LR) algorithm for multi-input multi-output detection in time-varying channels. The proposed scheme reduces the complexity by performing LR in a block-wise manner. The proposed scheme takes advantage of the temporal correlation of the channel matrices in a block and its impact on the lattice transformation matrices during the LR process. From this, the proposed scheme can skip a number of redundant LR processes for consecutive channel matrices and performs a single LR in a block. As the Doppler frequency decreases, the complexity reduction efficiency becomes more significant.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1839-1849
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• 1989

An optimal variable assignment algorithm is presented as a decomposition method of MVL functions. A given 3-valued combinational logic function is disintegrated into subfunction composed of the function dependant relation, then extracted implicant output elements from subfunctions are assigned to a T-gates. As a circuit implementation tool, a programmable integarated T-gate module is proposed, and the construction procedure of combinational MVL functions is systematized in each step. This method is expected to give properties of the systematic procedure, possibility of T-gate number reduction, unification of module, and flexibility of module composition. Specially variable decomposition method can be pointed out as an approach to solving the limitation problem of the input and output terminal number in VLSI implementations.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1880-1885
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• 1989

In this paper, a new approach for systolic array realizing the discrete cosine transform (DCT) based on discrete Fourier transform (DFT) of an input sequence is presented. The proposed array is based on a simple modified DFT(MDFT) version of the Goertzel algorithm combined with Kung's approach and is proved perfectly. This array requires N cells, one multiplier and takes N clock cycles to produce a complete N-point DCT and also is able to process a continuous stream of data sequences. We have analyzed the output signal-to-noise ratio(SNR) and designed the circuit level layout of one-PE chip. The array coefficients are static adn thus stored-product ROM's can be used in place of multipliers to limit cost as eliminate errors due to coefficients quantization.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.1
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• pp.136-146
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• 1995

In this paper, a Japanese morphological analyzer for Japanese to Korean Machine Translation System is designed. The analyzer reconstructs the Japanese input sentence into word phrases that include grammatical and dictionary informations. Thus we propose the algorithm to separate morphemes and then connect them by reference to a corresponding Korean word phrases. And we define the connector to control Japanese word phrases It is used in controlling the start and the end point of the word phrase in the Japanese sentence which is without a space. The proposed analyzer uses the analysis dictionary to perform more efficient analysis than the existing analyzer. And we can decrease the number of its dictionary searches. Since the analyzer, proposed in this paper, for Japanese to Korean Machine Translation System processes each word phrase in consideration of the corresponding Korean word phrase, it can generate more accurate Korean expressions than the existing one which places great importance on the generation of the entire sentence structure.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.4
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• pp.243-250
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• 2003

In this paper, the speed controller of permanent-magnet synchronous motor (PMSM) using the RBF neural (NN) disturbance observer is proposed. The suggested controller is designed using the input-output feedback linearization technique for the nominal model of PMSM and incorporates the RBF NN disturbance observer to compensate for the system uncertainties. Because the RBF NN disturbance observer which estimates the variation of a system parameter and a load torque is employed, the proposed algorithm is robust against the uncertainties of the system. Finally, the computer simulation is carried out to verify the effectiveness of the proposed method.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.5
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• pp.134-140
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• 1994

In this paper, an algorithm of CBAM(Combination Bidirectional Associative Memory) model proposes, analyzes and tests CBAM model `s performancess by simulating with recalls and recognitions of patterns. In learning-procedure each correlation matrix of training patterns is obtained. As each correlation matrix's some elements correspond to juxtaposition, all correlation matrices are merged into one matrix (Combination Correlation Matrix, CCM). In recall-procedure, CCM is decomposed into a number of correlation matrices by spiliting its elements into the number of elements corresponding to all training patterns. Recalled patterns are obtained by multiplying input pattern with all correlation matrices and selecting a pattern which has the smallest value of energy function. By using a CBAM model, we have some advantages. First, all pattern having less than 20% of noise can be recalled. Second, memory capacity of CBAM model, can be further increased to include English alphabets or patterns. Third, learning time of CBAM model can be reduced greatly because of operation to make CCM.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.10 s.352
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• pp.18-26
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• 2006

In this paper, we propose new beamforming algorithm which overcomes signal cancellation effect even high cross correlation existing between target and interfering signal. Using the proposed method, we show that direction of arrival (DOA) of interfering signal can be estimated using correlation matrix and the cross-correlation can be eliminated in the correlation matrix of input signal. The proposed method gives high performance enhancement compared with the spatial averaging method in our computer simulation results.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.7
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• pp.70-81
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• 1997

In this paper, we propose HMCNN(hybrid multiple component neural networks) that enhance performance of MCNN by adapting new pattern partitioning algorithm which can cluster many input patterns efficiently. Added neural network performs similar learning procedure that of kohonen network. But it dynamically determine it's number of output neurons using algorithms that decide self-organized number of clusters and patterns in a cluster. The proposed network can effectively be applied to problems of large data as well as huge networks size. As a sresutl, proposed pattern partitioning network can enhance performance results and solve weakness of MCNN like generalization capability. In addition, we can get more fast speed by performing parallel learning than that of other supervised learning networks.