• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2007.04a
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• pp.421-428
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• 2007

This paper discusses a fitness of the control on intersection network using fuzzy analytic hierachy process. The validity of control of traffic signal on intersection is phase, cycle of intersection. But the aigent of traffic intersection network is relative of intersection article. Therefor the aigent of traffic network intersection is before intersection passing vechile number, delayed vechile number. Fuzzy analytic hierachy process clears the grade of validity of the fixed cycle time controller and adaptive fixed cycle time and fuzzy traffic controller and proposes a new control type a traffic signal by this fuzzy analytic hierachy process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.824-831
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• 2014

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1222-1230
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• 2022

As the number of signal sources with low detectability by using various modulation techniques increases, research to classify signal modulation methods is steadily progressing. Recently, a Convolutional Neural Network (CNN) deep learning technique using FFT as a preprocessing process has been proposed to improve the performance of received signal classification in signal interference or noise environments. However, due to the characteristics of the FFT in which the window is fixed, it is not possible to accurately classify the change over time of the detection signal. Therefore, in this paper, we propose a CNN model that has high resolution in the time domain and frequency domain and uses wavelet transform as a preprocessing process that can express various types of signals simultaneously in time and frequency domains. It has been demonstrated that the proposed wavelet transform method through simulation shows superior performance regardless of the SNR change in terms of accuracy and learning speed compared to the FFT transform method, and shows a greater difference, especially when the SNR is low.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.164-171
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• 1996

We report the experimental resutls on AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with carbon-doped base structure. To characterize the output power, load-pull mehtod was employed. By characterizing the devices with HP8510C, we extracted the small-signal equivalent circuit. The HBTs were fabricated employing wet mesa etching and lift-off process of ohmic metals. the implementation of polyimide into the fabriction process was accomplished to obtain the lower dielectric constant resultig in significant reduction of interconnect routing capacitance. The fabricated HBTs with an emitter area of 6${\times}14{\mu}m^{2}$ exhibited current gain of 45, BV$_{CEO}$ of 10V, cut-off frequency of 30GHz and power gain of 1 3dBm. To extract the small signal equivalent circuit, the de-embedded method was applied for parasitic parameters and the calculation of circuit equations for intrinsic parameters.

• Journal of the Korea Society of Computer and Information
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• v.6 no.2
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• pp.108-115
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• 2001

SDH-based SHR networks are the reconfiguration process in case of failure and APS protocol used. In this study, addresses the maximum allowed recovery time in two fiber bidirectional networks. We analyse the APS protocol and derive the Processing time domains of each n order to cope with the maximum reconfiguration time of 50㎳, as specified in the ITU-T standard. We finally analyze the interleaved failures. One is the signal degrade then the signal failure, the other is the signal failure then the signal failure. Any case analysis is carried out. reconfiguration time can be guaranteed.

• Journal of the Korean Society for Nondestructive Testing
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• v.26 no.3
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• pp.174-180
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• 2006

Steam generator (SG) tubes are expanded inside tubesheet holes by using explosive or hydraulic methods to be fixed in a tubesheet. In the tube expansion process, it is important to minimize the crevice gap between expanded tube and tube sheet. In this paper, absolute and differential signals are computed by a numerical method for several different locations of tube expansion inside and outside a tubesheet and signal variations due to tubesheet, tube expansion and operating frequencies are observed. Results show that low frequency is good for detecting tubesheet location in both types of signals and high frequency is suitable for sizing of tube diameter as well as the detection of transition region. Also learned is that the absolute signal is good for measuring tube diameter, while the differential signal is good for locating the top of tubesheet and both ends of the transition region. In the case of mingled anomaly with tube expansion and tubesheet, low frequency inspection is found to be useful to analyze the mixed signal.

• Journal of Biomedical Engineering Research
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• v.17 no.3
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• pp.319-326
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• 1996

Clinical myography(EMG) is a technique for diagnosing neuromuscular disorders by analyzing the electrical signal that can be records by needle electrode during a muscular contraction. The EMG signal arises from electrical discharges that accompany the generation of force by groups of muscular fiber, and the analysis of EMG signal provides symptoms that can distinguish disorder of mLecle from disor- ders of nerve. One of the methods for analysis of EMG signal is to separate the individual discharge-the motor unit action potentials(MVAPS) - from EMG signal. But we can only observe the EMG signal that is a superimposed version of time delayed MUAPS. To obtain the information about MUAP(, i.e., position, firing number, magnitude etc), first of all, a method that can separate each MUAP from the EMG signal must be developed Although the methods for MUAP separation have been proposed by many researcherl they have required heavy computational burden. In this paper, we proposed a new method that has less computational burden and performs more reliable separation of superimposed EMG signal using wavelet filter which has multiresolution analysis as major property. As a result, we develope the separation algorithm of superimposed EMG signal which has less computational burden than any other researchers and exacutes exact separation process. The performance of this method has been discussed in the automatic resolving procedure which is neccessary to identify every firing of every motor unit from the EMG pattern.

• Proceedings of the Korean Nuclear Society Conference
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• 1995.10a
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• pp.197-202
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• 1995

When the process disturbance of nuclear power plant occurred, the operator should ensure plant safety, economy and identify the causes of disturbance. To accomplish these goals, operator should process a large amounts of information. Among these, alarms would be often in the operator's first indication of a plant state change or disturbance. To support limited information processing capability of operator, considerable works are under way to develop advanced alarm processing systems and to evaluate it. However, conventional evaluation method could provide just evaluation results but the design alternatives to enhance alarm system performance. To overcome problems associated with conventional evaluation methods of alarm system, signal detection theory(SDT) was introduced, and it was possible conclude that SDT could not only evaluate system but also suggest design alternatives for performance enhancement.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.98-107
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• 1993

This paper describes a design of a multi-bit oversampling noise-shaping D/A converter which achieves a resolution of 12 bits using oversampling technique. In the architecture the essential block which determines the whole accuracy is the analog internal D/A converter, and the designed charge-integration internal D/A converter adopts a differential structure in order to minimize the reduction of the resolution due to process variation. As the proposed circuit is driven by signal clocks which contains the information of the data variation from the noise-shaping coder, it minimizes the disadvantage of a charge-integration circuit in the time axis. In order to verify the circuit, it was integrated with the active area of 950$\times$650${\mu}m^{2}$ in a double metal 1.5-$\mu$m CMOS process, and testified that it can achieve a S/N ratio of 75 dB and a S/(N+D) ratio of 60 dB for the signal bandwidth of 9.6 kHz by the measurement with a spectrum analyzer.