• Journal of KIISE:Software and Applications
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• v.34 no.4
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• pp.303-316
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• 2007

Even though many approaches for reuse have been introduced, software engineers are still hesitating to reuse existing software components. Among various reasons for the phenomena, the most significant one is that existing approaches failed to give substantial benefit for the reduction of developers' effort in reusing software assets. To solve this problem, we introduce a custom reuse model utilizing diverse aspects of components specified by RAS and services oriented architecture. We also carried out a case study to demonstrate its feasibility and evaluated it by comparing it to an existing code-based software reuse process. The proposed reuse model helps in the reduction of effort in reusing existing components by decreasing the time for searching and understanding them. Compared to other approaches such as product line engineering, our approach for software reuse using MPC does not require much initial work for implementing the reuse model in different projects. It is of interest to software engineers who are worried about heavy investment, which can cause the delay in their usual development work. Furthermore, the proposed reuse model is not mutually exclusive with other approaches for software reuse such as CBSD or product line engineering. It can accelerate the benefits gained from them.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.7
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• pp.42-48
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• 2016

In this paper, a high-precision peak detector circuit that detects the output voltage information of a fly-back converter is proposed. The proposed design consists of basic analog elements with only one operational amplifier and three transistors. Because of its simple structure, the proposed circuit can minimize the delay time of the detection process, which has a strong impact on the precision of the regulation aspect of the fly-back converter. Furthermore, by using an amplifier and several transistors, the proposed detector can be fully integrated on-chip, instead of using discrete circuit elements, such as capacitors and diodes, as in conventional designs, which reduces the production cost of the fly-back converter module. In order to verify the performance of the proposed scheme, the peak detector was simulated and implemented by using a 0.35 m MagnaChip process. The gained results from the simulation with a sinusoidal stimulus signal show a very small detection error in the range of 0.3~3.1%, which is much lower than other reported detecting circuits. The measured results from the fabricated chip confirm the simulation results. As a result, the proposed peak detector is recommended for designs of high-performance fly-back converters in order to improve the poor regulation aspect seen in conventional designs.

• Journal of Satellite, Information and Communications
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• v.2 no.2
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• pp.48-52
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• 2007

Recently, the research of GPS receiver which uses the Software-Defined Radio(SDR) technique is being actively proceeded instead of traditional hardware-based receiver. The software-based GPS receiver indicates that the signal acquisition and tracking treated by the hardware-based platform are processed as the software technique through a microprocessor. In this paper, GPS software receiver is designed by using SDR technique and then the signal acquisition, tracking, and the navigation message decoding parts are verified through the PC-based simulation. Moreover, the efficient algorithms are developed about the signal acquisition and tracking parts in order to obtain the accurate pseudorange. Finally, the pseudorange is calculated through the relative channel delay received through the different satellite of L1 frequency band. GPS software receiver proposed in this paper will be included in the element of GPS/Galileo complex system of development target and will provide not only the method that verifies the performance for Galileo Sensor Station standard but also usability by providing various debugging environments.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.463-472
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• 2009

Real-time operating systems must have satisfying various conditions such as effective scheduling policies, minimized interrupt delay, resolved priority inversion problems, and its applications to be completed within desired deadline. The real-time operating systems, therefore, should be designed and developed to be optimal for these requirements. MicroC/OS-II, a kind of Real-time operating systems, uses the basic priority inheritance with a mutex to solve priority inversion problems. For the implementation of mutex, the kernel in an operating system should provide supports for numerous tasks with same priority. However, MicroC/OS-II does not provide this support for the numerous tasks of same priority. To solve this problem, MicroC/OS-II cannot but using priority reservation, which leads to the waste of unnecessary resources. In this study, we have dealt with new design a protocol, so called TPSP(Temporary Priority Swap Protocol), by an effective solution for above-mentioned problem, eventually enabling embedded systems with constrained resources environments to run applications.

• Journal of Convergence for Information Technology
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• v.10 no.10
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• pp.1-8
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• 2020

The need for storage, management, and retrieval techniques for alternative data has emerged as technologies based on data generated from business activities conducted by enterprises have emerged as the key to business success in recent years. Existing big data platform systems must load a large amount of data generated in real time without delay to process unstructured data, which is an alternative data, and efficiently manage storage space by utilizing a deduplication system of different storages when redundant data occurs. In this paper, we propose a multi-layer distributed data deduplication process system using the similarity of the Cuckoo hashing filter technique considering the characteristics of big data. Similarity between virtual machines is applied as Cuckoo hash, individual storage nodes can improve performance with deduplication efficiency, and multi-layer Cuckoo filter is applied to reduce processing time. Experimental results show that the proposed method shortens the processing time by 8.9% and increases the deduplication rate by 10.3%.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• The Journal of the Acoustical Society of Korea
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• v.22 no.2
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• pp.121-128
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• 2003

Acoustic Echo Cancellation(m) is very active research topic having many applications like teleconference and hands-free communication and it employs Double Talk Detector(DTD) to indicate whether the near-end speaker is active or not. However. the DTD is very sensitive to the variation of acoustical environment and it sometimes provides wrong information about the near-end speaker. In this paper, we are focusing on the development of robust DTD algorithm which is a basic building block for reliable AEC system. The proposed AEC system consists of delayless subband AEC and narrow-band DTD. Delayless subband AEC has proven to have excellent performance of echo cancellation with a low complexity and high convergence speed. In addition, it solves the signal delay problem in the existing subband AEC. On the other hand, the proposed narrowband DTD is operating on low frequency subband. It can take most advantages from the narrow subband such as a low computational complexity due to the down-sampling and the reliable DTD decision making procedure because of the low-frequency nature of the subband signal. From the simulation results of the proposed narrowband DTD and wideband DTD, we confirm that the proposed DTD outperforms the wideband DTD in a sense of removing possible false decision making about the near-end speaker activity.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.5
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• pp.63-71
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• 2011

In this paper, we propose a new real time image retargeting method which preserves the contents of an image. Since the conventional seam carving which is the well-known content-based image retargeting technology uses the dynamic programming method, the repetitive update procedure of the accumulation minimum energy map is absolutely needed. The energy map update procedure cannot avoid the processing time delay because of many operations by the image full-searching. The proposed method calculates the diffusion region of each seam candidates in the accumulation minimum energy map in order to reduce the update processing time. By using the diffusion region, several seams are extracted at the same time and the update number of accumulation energy map is reduced. Therefore, although the fast processing is possible, the quality of an image can be analogously maintained with an existing method. The experimental results show that the proposed method can preserve the contents of an image and adjust the image size on a real-time.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.10
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• pp.1-9
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• 2004

User-Perceived application-level performance is a key to the adoption and success of CDMA 2000. To predict this performance in advance, a detailed end-to-end simulation model of a CDMA network was built to include application traffic characteristics, network architecture, network element details, and protocol features. We assess the user application performance when a Radio Access Network (RAN) and a Core Network (CN) adopt different transport architectures such as ATM and If. For voice Performance, we found that the vocoder bypass scenario shows 8% performance improvement over the others. For data packet performance, we found that HTTP v.1.1 shows better performance than that of HTTP v.1.0 due to the pipelining and TCP persistent connection. We also found that If transport technology is better solution for higher FER environment since the IP packet overhead is smaller than that of ATM for web browsing data traffic, while it shows opposite effect to small size voice packet in RAN architecture. Though simulation results we showed that the 3G-lX EV system gives much better packet delay performance than 3G-lX RTT, the main conclusion is that end-to-end application-level performance is affected by various elements and layers of the network and thus it must be considered in all phases of the technology evolution process.