• Journal of the Korea Society of Computer and Information
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• v.21 no.1
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• pp.147-153
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• 2016

In this paper, we propose an efficient dynamic workload balancing strategy which improves the performance of high-performance computing system. The key idea of this dynamic workload balancing strategy is to minimize execution time of each job and to maximize the system throughput by effectively using system resource such as CPU, memory. Also, this strategy dynamically allocates job by considering demanded memory size of executing job and workload status of each node. If an overload node occurs due to allocated job, the proposed scheme migrates job, executing in overload nodes, to another free nodes and reduces the waiting time and execution time of job by balancing workload of each node. Through simulation, we show that the proposed dynamic workload balancing strategy based on CPU, memory improves the performance of high-performance computing system compared to previous strategies.

• Journal of the Korea Society of Computer and Information
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• v.21 no.1
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• pp.125-129
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• 2016

In this paper, we propose an efficient dynamic workload balancing strategy which improves the performance of high-performance computing system. The key idea of this dynamic workload balancing strategy is to minimize execution time of each job and to maximize the system throughput by effectively using system resource such as CPU, memory. Also, this strategy dynamically allocates job by considering demanded memory size of executing job and workload status of each node. If an overload node occurs due to allocated job, the proposed scheme migrates job, executing in overload nodes, to another free nodes and reduces the waiting time and execution time of job by balancing workload of each node. Through simulation, we show that the proposed dynamic workload balancing strategy based on CPU, memory improves the performance of high-performance computing system compared to previous strategies.

• Journal of Internet Computing and Services
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• v.6 no.1
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• pp.65-72
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• 2005

Flash memories are one of best media to support portable computers in mobile computing environment. The features of non-volatility, low power consumption. and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However. we need to Improve traditional transaction management scheme due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal. we devise a new scheme called flash-aware transaction management (FATM). FATM improves transaction performance by exploiting SRAM and W-Cache, We also propose a simulation model to show the performance of FATM. Based on the results of the performance evaluation, we conclude that FATM scheme outperforms the traditional scheme.

• Journal of the Korea Society of Computer and Information
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• v.13 no.5
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• pp.45-52
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• 2008

In this paper, we propose an efficient dynamic workload balancing strategy which improves the performance of high-Performance computing system. The key idea of this dynamic workload balancing strategy is to minimize execution time of each job and to maximize the system throughput by effectively using system resource such as CPU, memory. Also, this strategy dynamically allocates job by considering demanded memory size of executing job and workload status of each node. If an overload node occurs due to allocated job, the proposed scheme migrates job, executing in overload nodes, to another free nodes and reduces the waiting time and execution time of job by balancing workload of each node. Through simulation, we show that the proposed dynamic workload balancing strategy based on CPU, memory improves the performance of high-performance computing system compared to previous strategies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.746-753
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• 2001

GenBIST implemented in this paper is an automatic CAD tool, which can automatically generate circuitry in VerilogHDL code based on user defined information for the memory testing. While most commercial and conventional CAD tools adopt a method in which they make memory-testing algorithms as a library to generate circuitry, our tool can generate circuitry according to the user-defined algorithm, which makes application of various algorithms easier. In addition, memory BIST circuitry can be shared with other memories by supporting embedded memories in our tool. Also, extra pins for the memory testing are not requited when boundary scan technique is combined.

• 전기의세계
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• v.26 no.2
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• pp.78-83
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• 1977

The Newton-Raphson method has now gained widespread popularity in Load-flow calculationes. In this paper programming is developed with aims to improve the convergence characteristics, speed and memory requirements in the above method. The method of Load-flow calculations is performed by employing the MW-O/MVAR-V decoupling principle. To reduce the memory requirements and improve the speed of calculation the programming of the Optimally Ordered Triangular Factorization method is developed. Besides this, other measures are taken to reduce memory requirements and computing time and to improve reliability. KECO'S 48 Bus system was tested and the method suggested in this paper was proved to be faster than any other methods.

• Journal of Communications and Networks
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• v.16 no.4
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• pp.436-446
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• 2014

The high intensity of research and modeling in fields of mathematics, physics, biology and chemistry requires new computing resources. For the big computational complexity of such tasks computing time is large and costly. The most efficient way to increase efficiency is to adopt parallel principles. Purpose of this paper is to present the issue of parallel computing with emphasis on the analysis of parallel systems, the impact of communication delays on their efficiency and on overall execution time. Paper focuses is on finite algorithms for solving systems of linear equations, namely the matrix manipulation (Gauss elimination method, GEM). Algorithms are designed for architectures with shared memory (open multiprocessing, openMP), distributed-memory (message passing interface, MPI) and for their combination (MPI + openMP). The properties of the algorithms were analytically determined and they were experimentally verified. The conclusions are drawn for theory and practice.

• KIISE Transactions on Computing Practices
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• v.20 no.9
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• pp.519-524
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• 2014

The operating systems in the system architecture, which is integrated several applications and modular electronic devices in the same computing device, demand partitioning technology for safety. Thus, operation system requires partition scheduler for partition scheduling. When we design partition scheduler in embedded system, which has small memory and low performance, such as space system, we must consider not only performance but also memory. In this paper, we introduces a linux-based memory efficient partition scheduler using partition bitmap. This partition scheduler demands small memory space and produce low partition switching overhead. The prototype was executed on a LEON4 processor, which is the Next Generation Multicore Processor (NGMP) in the space sector. In evaluation, this prototype shows accuracy, additional memory space and low partition switching overhead.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.2
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• pp.207-211
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• 2010

Storage Class Memory (SCM) has both characteristics of non-volatility and random byte addressability. The advent of SCM can bring about novel and innovative features that are not possible in con ventional computing systems. This paper suggests a new system design that turns on/off a system instantly. To do this, we replace the main memory with SCM to retain the volatile system states as the system is turned off. We implement our prototype in an embedded environment and measure its system on/off time.

• Electronics and Telecommunications Trends
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• v.35 no.3
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• pp.55-65
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• 2020

With the development of nonvolatile memory technology, Intel has released the Optane datacenter persistent memory module (DCPMM) that can be deployed in the dual in-line memory module. The results of research and experiments on Optane DCPMMs are significantly different from the anticipated results in previous studies through emulation. The DCPMM can be used in two different modes, namely, memory mode (similar to volatile DRAM: Dynamic Random Access Memory) and app direct mode (similar to file storage). It has buffers in 256-byte granularity; this is four times the CPU (Central Processing Unit) cache line (i.e., 64 bytes). However, these properties are not easy to use correctly, and the incorrect use of these properties may result in performance degradation. Optane has the same characteristics of DRAM and storage devices. To take advantage of the performance characteristics of this device, operating systems and applications require new approaches. However, this change in computing environments will require a significant number of researches in the future.