• The KIPS Transactions:PartC
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• v.12C no.2 s.98
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• pp.267-280
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• 2005

In this paper, we implement and verify XMIP integrating IETF Mobile IP and the Explicit Multicast mechanism for a great number of small group multicast communications. U a source node sends Xcast packets explicitly inserting destination nodes into the headers, each Xcast router decides routes and forwards the packets toward each destination node based on unicast routing table without the support of multicast trees. n is a straightforward and simple multicast mechanism just based on a unicast routing table without maintaining multicast states because of the inheritance from the Explicit Multicast mechanism. This research modifies and extends the functionality of IETF Mobile IP's mobility agents, such as HA/FA to HA+/FA+ respectively, considering interworking with Xcast networks. Xcast packets captured by HA+ are forwarded into X-in-X tunnel interfaces for each FA+ referred to the binding table of HA.. This X-in-X tunneling mechanism can effectively solve the traffic concentration problem of IETF Mobile IP multicast services. Finally WLAN-based testbed is built and a multi-user Instant messenger system is developed as a Xcast application for finally verify the feasibility of the implemented XMIP/Xcast protocols.

• Proceedings of the Earthquake Engineering Society of Korea Conference
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• 2006.03a
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• pp.527-534
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• 2006

A real-time hybrid method, in which the experimental implementation and the numerical computation of a structure are simultaneously carried out in real-time and combined on-line, has been used as a dynamic testing technique of structure to investigate its dynamic behaviors. In this paper, an experimental hybrid method, which implements the earthquake response control of a building structure with a TLD by using only a TLD as an experimental part, is proposed and is experimentally verified through a shaking table test. In the proposed methodology, the whole building structure with a TLD is divided into the upper TLD and the lower structural parts as experimental and numerical substructures, respectively. At the moment, the control force acting between their interface is measured from the experimental TLD with shear-type load-cell which is mounted on shaking table. Shaking table vibrates the upper experimental TLD with the response calculated from the numerical substructure, which is subjected to the excitations of the measured interface control force at its top story and an earthquake input at its base. The experimental results show that the conventional method, in which both a TLD and a building model are physically manufactured and are tested, can be replaced by the proposed methodology with a simple experimental installation and a good accuracy for evaluating the control performance of a TLD.

• Journal of Korean Society of Archives and Records Management
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• v.22 no.2
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• pp.51-73
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• 2022

Currently, an implementation plan of administrative information dataset record management has been prepared; however, analyzing the specificity of various administrative information systems and preparing a reasonable level of management reference table by applying about 1.3% (EA portal registration system: 16,199, consulting system: 214) has its limitations. This study started by recognizing the importance of the records management environment in administrative information datasets. Based on the described information, the current records management environment was analyzed by dividing the six areas of the management reference table of the picture archiving and communication system (PACS) into three groups. Thus, a systematic environmental improvement model was proposed, enhancing the effectiveness of dataset records management in the field. Although there is a limitation in analyzing one of the dataset records management environments of various institutions, it is intended to help broaden the horizons of records management research.

• Journal of Wellbeing Management and Applied Psychology
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• v.6 no.3
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• pp.13-18
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• 2023

Purpose: The small-scale environmental impact assessment has been in operation since its implementation in August 2000, and is a system that meets the purpose of sustainable development in consideration of the environment in areas requiring conservation. However, when preparing a small environmental impact assessment report, the contents of the reduction measures are too qualitative, or reports are prepared to simply list the compliance stipulated by individual laws, and the contents of consultations prepared by consultative agencies and review agencies are not much different. In addition, the direction of consultation on development projects for similar locations of the same project type is frequently changed by reflecting the subjective judgment of the consultative officer of the Ministry of Environment (Environment Agency). Therefore, this study attempted to improve the establishment of measures to reduce the existing simple listing of qualitative contents and the inconsistent presentation of review opinions by consultative agencies and review agencies. Research design, data and methodology: The research method extracted absolute evaluation items and relative evaluation items among small environmental impact assessment items, analyzed and presented detailed items, and prepared a distribution table for each section according to the details of the relative evaluation items, and presented them as a table. Results: This study was conducted to derive uniform results with objective indicators in the preparation and consultation process of a small-scale environmental impact assessment. Conclusions: Once a quantitative evaluation is established, the consultant can objectively determine and process the environmental impact.

• The Journal of the Acoustical Society of Korea
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• v.23 no.8
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• pp.554-561
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• 2004

As the technologies of semiconductor and multimedia communication have been improved. the high-quality video and the multi-channel audio have been highlighted. MPEG Audio Layer 3 decoder has been implemented as a Processor using a standard. Since the synthesis filter of MPEG-1 Audio Layer 3 decoder requires the most outstanding operation in the entire decoder. the synthesis filter that can reduce the amount of operation is needed for the design of the high-speed processor. Therefore, in this paper, the synthesis filter. the most important part of MPEG Audio, is materialized in FPGA using the method of DAULT (distributed arithemetic look-up table). For the design of high-speed synthesis filter, the DAULT method is used instead of a multiplier and a Pipeline structure is used. The Performance improvement by 30% is obtained by additionally making the result of multiplication of data with cosine function into the table. All hardware design of this Paper are described using VHDL (VHIC Hardware Description Language) Active-HDL 6.1 of ALDEC is used for VHDL simulation and Synplify Pro 7.2V is used for Model-sim and synthesis. The corresponding library is materialized by XC4013E and XC4020EX. XC4052XL of XILINX and XACT M1.4 is used for P&R tool. The materialized processor operates from 20MHz to 70MHz.

• Journal of the Korea Society of Computer and Information
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• v.24 no.11
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• pp.127-133
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• 2019

SQL is the most common language in data processing. Therefore, most of the colleges offer SQL in their curriculum. In this research, an auto scoring SQL test is proposed for the efficient results of SQL education. The system was treated with algorithms instead of using expensive DBMS(Data Base Management System) for automatic scoring, and satisfactory results were produced. For this system, the test question bank was established out of 'personnel management' and 'academic management'. It provides users with different sets of test each time. Scoring was done by dividing tables into two sections. The one that does not change the table(select) and the other that actually changes the table(update, insert, delete). In the case of a search, the answer and response were executed at first and then the results were compared and processed, the user's answers are evaluated by comparing the table with the correct answer. Modification, insertion, and deletion of table actually changes the data table, so data was restored by using ROLLBACK command. This system was implemented and tested 772 times on the 88 students in Computer Information Division of our college. The results of the implementation show that the average scoring time for a test consisting of 10 questions is 0.052 seconds, and the performance of this system is distinguished considering that multiple responses cannot be processed at the same time by a human grader, we want to develop a problem system that takes into account the difficulty of the problem into account near future.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12B
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• pp.2249-2261
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• 1999

In this paper, we describe the design and implementation of the Label Distribution Protocol (LDP) for Multiprotocol Label Switching System. We review the implementation issues of LDP that is required to make a gigabit switched router, and propose a detail design of it. We present the data structures and procedures for the LDP as a result, which are based on IETF standard. We present design issues for applying this to carrier class products. The implemented protocol could afford 40,000 entries of the IP routing table that is required for deploying this system to commercialized data network. Furthermore this system implemented using the standard API of Unix, as a result, it has portability. By implementing LDP based on the international standard and these implementation issues, we expect that the implemented LDP will be interoperable with other commercialized products. We prove the validity of the design of the LDP through prototyping, and also verify the prototype with the specification using the process algebra and the performance analysis.

• Journal of Internet Computing and Services
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• v.6 no.6
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• pp.117-125
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• 2005

The dominator tree presents the dominance frontier from directed graph to the tree. we present the effective algorithm for constructing the dominator tree from arbitrary directed graph. The reducible flow graph was reduced to dominator tree after dominator calculation. And the irreducible flow graph was constructed to dominator-join graph using join-edge information of information table. For reducing the dominator tree from dominator-join graph, we implement the effective sequency reducible algorithm and delay reducible algorithm. As a result of implementation, we can see that the delay reducible algorithm takes less execution time than the sequency reducible algorithm. Therefore, we can reduce the flow graph to dominator tree effectively.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1577-1580
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• 2004

This paper proposes a design and implementation of transversal adaptive digital filter using LMS (Least Mean Squares) adaptive algorithm. The filter structure is based on Distributed Arithmetic (DA) which is able to calculate the inner product by shifting and accumulating of partial products and storing in look-up table, also the desired adaptive digital filter will be multiplierless filter. In addition, the hardware implementation uses VHDL (Very high speed integrated circuit Hardware Description Language) and synthesis using FLEX10K Altera FPGA (Field Programmable Gate Array) as target technology and uses Leonardo Spectrum and MAX+plusII program for overall development. The results of this design are shown that the speed performance and used area of FPGA. The experimental results are presented to demonstrate the feasibility of the desired adaptive digital filter.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.758-761
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• 2004

This paper proposes a design and implementation of multiplierless digital PID (Proportional-Integral-Derivative) controller using FPGA (Field Programmable Gate Array) for controlling the speed of DC motor in digital system. The multiplierless PID structure is based on Distributed Arithmetic (DA). The DA is an efficient way to compute an inner product using partial products, each can be obtained by using look-up table. The PID controller is designed using MATLAB program to generate a set of coefficients associated with a desired controller characteristics. The controller coefficients are then included in VHDL (Very high speed integrated circuit Hardware Description Language) that implements the PID controller onto FPGA. MATLAB program is used to activate the PID controller, calculate and plot the time response of the control system. In addition, the hardware implementation uses VHDL and synthesis using FLEX10K Altera FPGA as target technology and use MAX+plusII program for overall development. Results in design are shown the speed performance and used area of FPGA. Finally, the experimental results can be shown when compared with the simulation results from MATLAB.