• Journal of Power Electronics
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• 제15권5호
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• pp.1235-1243
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• 2015

This paper presents a modified Space Vector Pulse Width Modulation Technique (SVPWM), which solves the well-known problem of voltage imbalance in the capacitors of a single-phase multilevel inverter. The proposed solution is based on the measurement of DC voltage levels at each capacitor of the inverter DC bus. The measurements are then used to adjust the size of the active vectors within the SVPWM algorithm to keep the voltage waveform sinusoidal regardless of any voltage imbalance on the DC link capacitors. When a voltage deviation exceeds a predetermined hysteresis band, the correspondent voltage vector is restricted to restore the voltage level to an acceptable threshold. Hence, the need for external voltage regulators for the voltage capacitors is eliminated. The functionality of the proposed algorithm is successfully demonstrated through simulations and experiments on a grid tied application.

• 전력전자학회논문지
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• 제27권4호
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• pp.348-355
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• 2022

A bipolar DC distribution system suffers from an imbalance in voltages when asymmetric loads are connected at the outputs. Dedicated voltage balancers are required to address the imbalance in bipolar voltage levels. However, additional components eventually increase the cost and decrease the efficiency and power density of the system. Therefore, to deal with the imbalance in output voltages without adding any extra components, this study presents a coupled inductor-based voltage balancing technique with a dual-output CLL resonant converter. The proposed coupled inductor does not require extra magnetic components to balance the output voltages because it is the result of resonant inductors of the CLL tank circuit. It can also avoid complex control schemes applied to voltage balancing. Moreover, with the proposed coupled inductor, the CLL converter acquires good features including zero voltage and zero current switching. Detailed analysis of the proposed coupled inductor is presented with different load conditions. A 3.6-kW hardware prototype was built and tested to validate the performance of the proposed coupled inductor-based voltage balancing technique.

• 전기학회논문지
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• 제67권2호
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• pp.209-215
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• 2018

This paper present a 7-level PWM inverter adopting voltage balancing control to series-connected input capacitors. The prior proposed 7-level PWM inverter consists of dc input source, three series-connected capacitors, two bidirectional switch modules, and an H-bridge. This circuit topology is useful to increase the number of output voltage levels, however it fails to generate 7-level in output voltage without consideration for voltage balancing among series-connected capacitors. Capacitor voltage imbalance is caused on the different period between charging and discharging of capacitor. To solve this problem, we uses the amplitude modulation of carrier wave, which is used to produce the center output voltage level. To verify the validity of the proposed control method, we carried out computer-aided simulation and experiments using a prototype.

• Journal of Power Electronics
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• 제16권3호
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• pp.823-831
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• 2016

A high-efficiency method is proposed to suppress magnetic core imbalance in phase-shifted full-bridge (PSFB) converters. Compared with conventional solutions, such as controlling peak current mode (PCM) or adding DC blocking capacitance, the proposed method has several advantages, such as lower power loss and smaller size, because the additional current sensor or blocking capacitor is removed. A time domain model of the secondary side is built to analyze the relationship between transformer core imbalance and cathode voltage of secondary side rectifiers. An approximate control algorithm is designed to achieve asymmetric phase control, which reduces the effects of imbalance. A 60 V/15 A prototype is built to verify the proposed method. Experimental results show that the numerical difference of primary side peak currents between two adjacent cycles is suppressed from 2 A to approximately 0 A. Meanwhile, compared with the PCM solution, the efficiency of the PSFB converter is slightly improved from 93% to 93.2%.

• Journal of Power Electronics
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• 제16권4호
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• pp.1551-1564
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• 2016

The high penetration level of inverter-based distributed generation (DG) power plants is challenging the low-voltage ride-through requirements, especially under unbalanced voltage sags. Recently, a flexible injection of both positive- (PS) and negative-sequence (NS) reactive currents has been suggested for the next generation of grid codes. This can enhance the ancillary services for voltage support at the point of common coupling (PCC). In light of this, considering distant grid faults that occur in a mainly inductive grid, this paper proposes a complete voltage support control scheme for the interface inverters of medium or high-rated DG power plants. The first contribution is the development of a reactive current reference generator combining PS and NS, with a feature to increase the PS voltage and simultaneously decrease the NS voltage, to mitigate voltage imbalance. The second contribution is the design of a voltage support control loop with two flexible PCC voltage set points, which can ensure continuous operation within the limits required in grid codes. In addition, a current saturation strategy is also considered for deep voltage sags to avoid overcurrent protection. Finally, simulation and experimental results are presented to validate the effectiveness of the proposed control scheme.

• Journal of Power Electronics
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• 제15권2호
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• pp.504-517
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• 2015

This paper presents a novel switching voltage model and an offset-based pulse width modulation (PWM) scheme for multilevel inverters with unbalanced DC sources. The switching voltage model under a DC voltage imbalance will be formulated in general form for multilevel neutral-point-clamped topologies. Analysis of the reference switching voltages from active and non-active switching voltage components in abc coordinates can enable voltage implementation for an unbalanced DC-source condition. Offset voltage is introduced as an indispensable variable in the switching voltage model for multilevel voltage-source inverters. The PWM performance is controlled through the design of two offset components in a subsequence. One main offset may refer to the common mode voltage, and the other offset restricts its effect on the quality of PWM control in related DC levels. The PWM quality can be improved as the switching loss is reduced in a discontinuous PWM mode by setting the local offset, which is related to the load currents. The validity of the proposed algorithm is verified by experimental results.

• 전기학회논문지
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• 제66권11호
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• pp.1584-1590
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• 2017

This paper presents a implementation method of reliable speed limitation controller considering motor parameter variation in high speed operation. In spinning process of drum washing machine, speed increase has to be limited when unallowable imbalance mass is detected. Otherwise, severe noise and vibration can happen because noise and vibration are proportional to imbalance mass. To detect imbalance mass, d-axis current magnitude is used. However, we have to compensate for back-emf and power supply variation by means of detecting them because d-axis current is affected by both of them. On the other hand, we have to carefully estimate back-emf because back-emf is affected by stator resistance variation and inverter voltage error. Stator resistance variation can happen by manufacturing process for mass production or temperature variation in running. And there are inverter voltage errors between command voltage from micro-computer to inverter and real voltage from inverter to motor because of rising and falling time delay and turn-on resistance of power semiconductor switch. To solve this problem, we propose 2-step align current injection method which is to inject step-wise current right before starting. By this method, we can simply obtain stator resistance by ratio of voltage without inverter voltage error and current, and we can measure inverter voltage error. So we can obtain more exact model current, and then by simple calculation with compensation gain, we can estimate more accurate motor back-emf. We show that this method works well. It is verified through experiments.

• 한국태양에너지학회 논문집
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• 제37권6호
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• pp.1-12
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• 2017

The DC link of Grid-Connected 3-Phase 3-Level T-type Photovoltaic PCS (PV-PCS) consists of two series connected capacitors for using their neutral voltage. The mismatch between two capacitor characteristics and transient states happened in load change cause the imbalance of neutral voltage. As a result, PV-PCS performance is degraded and the system becomes unstable. In this paper, a mathematical model for analyzing the imbalance of neutral voltage is derived and a compensation method using offset voltage is proposed, where offset voltage adjusts the applying time of P-type and N-type small vectors. The validity of the proposed methods is verified by simulation and experiment.

• 한국전기전자재료학회논문지
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• 제27권10호
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• pp.613-617
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• 2014

This paper was analyzed electrical characteristics of super junction power MOSFET considering to charge imbalance. We extracted optimal design and process parameter at -15% of charge imbalance. Considering extracted design and process parameters, we fabricated super junction MOSFET and analyzed electrical characteristics. We obtained 600~650 V breakdown voltage, $224{\sim}240m{\Omega}$ on resistance. This paper was showed superior on resistance of super junction MOSFET. We can use for automobile industry.

• 전기전자학회논문지
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• 제23권1호
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• pp.1-8
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• 2019

본 논문에서는 18650 원통형 NCA 리튬이온 배터리로 구성된 고출력 직렬 배터리로 다양한 C-rate의 전기적 특성을 테스트한다. 테스트를 통해 추출한 14S1P 배터리 팩의 방전 용량 데이터와 4S1P 배터리 팩의 EV cycle 데이터를 통해 C-rate의 변화에 따른 전기적 특성을 분석한다. 분석을 통해 얻은 데이터를 기반으로 C-rate에 따른 방전용량 실험의 셀 간 전압 편차와 EV cycle 실험의 셀 간 전압 편차를 다중선형회귀 모델로 추정하여 선형적인 특징을 가진 데이터와 비선형적인 특징을 가진 데이터에 대한 각각의 추정성능을 검증한다. 모델의 추정성능을 검증하기 위해 추정 데이터와 실제 데이터의 RMSE를 구해 알고리즘의 정확성을 평가한다. 논문의 결과는 14S1P 배터리 팩의 방전 용량의 셀 간 전압 불균형과 4S1P 배터리 팩의 EV cycle의 셀 간 전압 불균형 중 선형적인 데이터인 방전 용량의 셀 간 불균형 데이터의 추정 성능이 더 뛰어난 것을 검증하는데 기여한다.