• Current Optics and Photonics
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• v.2 no.5
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• pp.453-459
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• 2018

We have developed a high-performance signal-processing and image-rendering heterogeneous computation system for optical coherence tomography (OCT) on mobile processor. In this paper, we reveal it by demonstrating real-time OCT image processing using a Snapdragon 800 mobile processor, with the introduction of a heterogeneous image visualization architecture (HIVA) to accelerate the signal-processing and image-visualization procedures. HIVA has been designed to maximize the computational performances of a mobile processor by using a native language compiler, which targets mobile processor, to directly access mobile-processor computing resources and the open computing language (OpenCL) for heterogeneous computation. The developed mobile image processing platform requires only 25 ms to produce an OCT image from $512{\times}1024$ OCT data. This is 617 times faster than the naïve approach without HIVA, which requires more than 15 s. The developed platform can produce 40 OCT images per second, to facilitate real-time mobile OCT image visualization. We believe this study would facilitate the development of portable diagnostic image visualization with medical imaging modality, which requires computationally expensive procedures, using a mobile processor.

• Journal of IKEEE
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• v.20 no.1
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• pp.89-93
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• 2016

In this paper, we proposed SIMT based Image Signal Processor which can apply various image preprocessing algorithms and allow parallel processing of application programs such as image recognition. Conventional ISP has the hard-wired image enhancement algorithm of which the processing speed is fast, but there was difficult to optimize performance depending on various image processing algorithms. The proposed ISP improved the processing time applying SIMT architecture and processed a variety of image processing algorithms as an instruction based processor. We used Xilinx Virtex-7 board and the processing time compared to cell multicore processor, ARM Cortex-A9, ARM Cortex-A15 was reduced by about 71 percent, 63 percent and 33 percent, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1737-1744
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• 2010

The Image sensor needs various image processing to improve image quality. ISP(Image Signal Processor) performs various image processing. Conventional vision cameras have own software ISP functions and perform in PC instead of using commercial ISP chips. However these methods have problems such as large computation for image processing. In this paper, we proposed ISP that significantly reduced chip area by efficient sharing of hardware and software. Large operation blocks are designed to hardware for high performances, and we used hardware simultaneously with software considering the size of the hardware. The implemented ISP can process VGA(640*4800) images and has 91450 gate sizes in 0.35um process.

• Journal of the Institute of Convergence Signal Processing
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• v.17 no.1
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• pp.26-31
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• 2016

In this paper, we propose an image quality evaluation system for compact camera module and assess the effect of optical performance improvement for proposed anti-halation disk in small lens. We develop a image quality evaluation system for quality estimation of camera module image. And we also develop a program to control register in image signal processor. Finally the resolution, brightness, and color reproduction performances were evaluated image quality comparison between conventional and proposed camera module using developed quality evaluation system and ISP register control program.

• Korean Journal of Remote Sensing
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• v.21 no.6
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• pp.483-491
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• 2005

SAR signal processing technique has been considered a crucial technical part in order to generate an image from radar signal data and ADD (Agency for Defense Development) has focused on this area for years to develope our own SAR Processor for various SAR systems (Radarsat, ERS, KOMSAR). In this paper, we investigated major techniques related to generation of SAR images and developed ASPR (ADD SAR Processor for Radarsat) practically using the commercial Radarsat-1 radar signal data (RAW). We demonstrated the performance of the ASPR in comparison with the image generated by MDA and Vexcel's SAR Processor (FOCUS).

• 제어로봇시스템학회:학술대회논문집
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• 1993.10a
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• pp.685-691
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• 1993

This paper introduces a PC-based image data processing unit that is composed of preprocessor board and main processor board; The preprocessor contains Inmos A110 processor and efficient H/W architecture for fast mask/logic operations at the speed of video signal rate. It is controlled by the main processor which communicates with the host PC. The main processor board contains TI TMS320C31 digital signal processor, and can access the frame memory of the processor for extra S/W tasks. We test 3*3, 5*5 masks and logic operations on 386/486/DSP and compare the result with that of the proposed unit. The result shows ours are extremely faster than conventional CPU based approach, that is, over several hundred times faster than even DSP.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.103-111
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• 2007

In this paper, we propose a VLSI architecture of hardware optimized high quality image signal processor for a Single-chip CMOS Image Sensor(CIS). The Single-chip CIS is usually used for mobile applications, so it has to be implemented as small as possible while maintaining the image quality. Several image processing algorithms are used in ISP to improve captured image quality. Among the several image processing blocks, demosaicing and image filter are the core blocks in ISP. These blocks need line memories, but the number of line memories is limited in a low cost Single-chip CIS. In our design, high quality edge-adaptive and cross channel correlation considered demosaicing algorithm is adopted. To minimize the number of required line memories for image filter, we share the line memories using the characteristics of demosaicing algorithm which consider the cross correlation. Based on the proposed method, we can achieve both high quality and low hardware complexity with a small number of line memories. The proposed method was implemented and verified successfully using verilog HDL and FPGA. It was synthesized to gate-level circuits using 0.25um CMOS standard cell library. The total logic gate count is 37K, and seven and half line memories are used.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1449-1453
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• 1987

A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1147-1154
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• 2011

Auto exposure (AE) in image signal processor (ISP) controls brightness of input image to the proper brightness when it is too dark or bright. But conventional AEs often fail to get proper brightness since AE controls only average brightness of image. Especially in applications that require object recognition, it cannot be solved the problem by AE of ISP. In this paper proposes Histogram Equalization (HE) processes that is the alternative of AE. It also proposes proper method to realize hardware and compensate HE problems conventional by using simple calculation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.3
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• pp.177-183
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• 2018

Currently, digital signal processing systems are used extensively in image processing, audio processing, filtering, and equalizations, etc. In addition, the importance of DRAM, which has a great influence on the performance of an digital signal processor has been increased, making research on DRAM actively conducted in industry and academia. Therefore, it is important to have a more accurate DRAM model in order to obtain reliable results when evaluating the performance of a digital signal processor through simulation. In this paper, we developed a digital signal processor simulator capable of inter-working with a DRAM simulator. With the simulator, we analyzed the influence of the DRAM model which operates correctly on a cycle-by-cycle basis, on the performance of the digital signal processor by using the UTDSP digital signal benchmark.