• Journal of the Korea Society of Computer and Information
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• v.18 no.5
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• pp.1-8
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• 2013

Smartphone enables diverse applications to be used in mobile environments. In spite of the high performance of smartphones, battery life has become one of the major constraints in mobility. Therefore, power efficiency of the smartphone is one of the most important factors in determining the efficiency of the smartphone. In this paper, in order to analyze the power efficiency of the smartphone, we have various experiments according to several configuration parameters such as processor, display and OS. We also use diverse applications. As a result, power consumption is dependent on the processor complexity and display size. However, power consumption shows the unpredictable pattern according to the OS. Smartphone using android OS consumes high power when internet and image processing applications are executed, but It consumes low power when music and camera applications are executed. In contrary, smartphone based on iOS consumes high power when game and internet applications are executed but it consumes low power when camera and processing applications are executed. In general, smartphone using iOS is more power efficient than smartphone based on android OS, because smartphone using iOS is optimized in the perspective of the hardware and OS.

• Journal of the Korean Vacuum Society
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• v.20 no.1
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• pp.22-29
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• 2011

An infrared thermographic imaging module of [$320{\times}256$] focal-plane array (FPA) based on [InAs/GaSb] strained-layer superlattice (SLS) was fabricated, and its images were demonstrated. The p-i-n device consisted of an active layer (i) of 300-period [13/7]-ML [InAs/GaSb]-SLS and a pair of p/n-electrodes of (60/115)-period [InAs:(Be/Si)/GaSb]-SLS. FTIR photoresponse spectra taken from a test device revealed that the peak wavelength (${\lambda}_p$) and the cutoff wavelength (${\lambda}_{co}$) were approximately $3.1/2.7{\mu}m$ and $3.8{\mu}m$, respectively, and it was confirmed that the device was operated up to a temperature of 180 K. The $30/24-{\mu}m$ design rule was applied to single pixel pitch/mesa, and a standard photolithography was introduced for [$320{\times}256$]-FPA fabrication. An FPA-ROIC thermographic module was accomplished by using a $18/10-{\mu}m$ In-bump/UBM process and a flip-chip bonding technique, and the thermographic image was demonstrated by utilizing a mid-infrared camera and an image processor.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.

• Investigative Magnetic Resonance Imaging
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• v.7 no.1
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• pp.12-21
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• 2003

Purpose : In order to overcome limitations in the existing conventional spectrometer, a new spectrometer with advanced functionalities is designed and implemented. Materials and Methods : We designed a spectrometer using the TMS320C6701 DSP capable of 1 giga floating point operations per second (GFLOPS). The spectrometer can generate continuously varying complicate gradient waveforms by real-time calculation, and select image plane interactively. The designed spectrometer is composed of two parts: one is DSP-based digital control part, and the other is analog part generating gradient and RF waveforms, and performing demodulation of the received RF signal. Each recover board can measure 4 channel FID signals simultaneously for parallel imaging, and provides fast reconstruction using the high speed DSP. Results : The developed spectrometer was installed on a 1.5 Tesla whole body MRI system, and performance was tested by various methods. The accurate phase control required in digital modulation and demodulation was tested, and multi-channel acquisition was examined with phase-array coil imaging. Superior image quality is obtained by the developed spectrometer compared to existing commercial spectrometer especially in the fast spin echo images. Conclusion : Interactive control of the selection planes and real-time generation of gradient waveforms are important functions required for advanced imaging such as spiral scan cardiac imaging. Multi-channel acquisition is also highly demanding for parallel imaging. In this paper a spectrometer having such functionalities is designed and developed using the TMS320C6701 DSP having 1 GFLOPS computational power. Accurate phase control was achieved by the digital modulation and demodulation techniques. Superior image qualities are obtained by the developed spectrometer for various imaging techniques including FSE, GE, and angiography compared to those obtained by the existing commercial spectrometer.

• Journal of the Korea Society of Computer and Information
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• v.27 no.11
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• pp.181-190
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• 2022

In this paper, we use a LiDAR sensor and an image camera to detect a left-turning waiting vehicle in two ways, unlike the existing image-type or loop-type left-turn detection system, and a left-turn traffic signal corresponding to the waiting length of the left-turning lane. A system that can efficiently assign a system is introduced. For the LiDAR signal transmitted and received by the LiDAR sensor, the left-turn waiting vehicle is detected in real time, and the image by the video camera is analyzed in real time or at regular intervals, thereby reducing unnecessary computational processing and enabling real-time sensitive processing. As a result of performing a performance test for 5 hours every day for one week with an intersection simulation using an actual signal processor, a detection rate of 99.9%, which was improved by 3% to 5% compared to the existing method, was recorded. The advantage is that 99.9% of vehicles waiting to turn left are detected by the LiDAR sensor, and even if an intentional omission of detection occurs, an immediate response is possible through self-correction using the video, so the excessive waiting time of vehicles waiting to turn left is controlled by all lanes in the intersection. was able to guide the flow of traffic smoothly. In addition, when applied to an intersection in the outskirts of which left-turning vehicles are rare, service reliability and efficiency can be improved by reducing unnecessary signal costs.

• Journal of Digital Convergence
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• v.12 no.4
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• pp.311-318
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• 2014

This paper is to introduce a lighting source controller using high brightness LED to create a clear and reliable condition for an accurate measurement and testing, which is a core technology in clinical image system and mechanical automation system. This controller is designed to supply a stable power in a constant-current system by installing a high brightness LED driver, and to improve the reproducibility of brightness by using 32-bit ARM processor core, dividing brightness quantity into 256 levels, making the remote control and the external interface possible, and preventing and digitizing the brightness inaccuracy caused by errors of resistance values. This controller enables the lighting range to be wide and possible in a low lighting level compared to analog, adds the RS-485 communication function, and makes it for the users to control the on-off function and the dimming level by receiving date from an external device.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.108-116
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• 2013

Many algorithms have been introduced to improve performance by using massively parallel systems, which consist of several hundreds of processors. A typical example is a GPU system of many processors which uses shared memory. In the case of image filtering algorithms, which make references to neighboring points, the shared memory helps improve performance by frequently accessing adjacent pixels. However, using shared memory requires rewriting the existing codes and consequently results in complexity of the codes. Recent GPU systems support both L1 and L2 cache along with shared memory. Since the L1 cache memory is located in the same area as the shared memory, the improvement of performance is predictable by using the cache memory. In this paper, the performance of cache and shared memory were compared. In conclusion, the performance of cache-based algorithm is very similar to the one of shared memory. The complexity of the code appearing in a shared memory system, however, is resolved with the cache-based algorithm.

• Journal of the Korean Society for Nondestructive Testing
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• v.13 no.2
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• pp.20-30
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• 1993

Electric Speckle Pattern Interferometry (ESPI) using a CW-laser, a video system and an image processor was applied to the thermal coefficient measurements on free thermal expansions at high temperatures : ESPI provides the distribution of in-plane displacement resolved in a preselected direction. ESPI retains the merits of little or no surface preparation, no contact with the surface and the real-time presentation of interference fringes. Appling ESPI at high temperatures, several problem which caused the reduction of fringe visibility were encountered. The problem on the turbulence in the hot air surrounding high temperature objects will be solved by using a vacuum chamber. The background radiations from the objects were suppressed considerably by an interference filter. The problem on the oxidation of the object surface could't be solved. The interference fringe, whose spacings were calculated by FFT to avoid human error, were observable up to $800^{\circ}C$. The results measured by ESPI were nearly equal to the data which have already been published, up to about $800^{\circ}C$.

• Journal of Sensor Science and Technology
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• v.8 no.1
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• pp.69-79
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• 1999

The research and implementation was preformed on high-resolution CCTV camera with CCD exclusive DSP conventional analog signal processor CCTV camera has its limit on auto exposure(AE), auto white balance(AWB), back light compensation(BLC) processing, severe distortion and noise of image, manual control parameter setting, etc. In our study, to resolve the problems in conventional CCTV camera, we made it possible to control AE, AWB, BLC automatically by the use of the DSP, which are used exclusively in the CCD camera produced domestically, and the microcontroller. And we utilized the function of screen display of microcontroller for the user-friendly interface to control CCD camera. And the electronic variable resister(EVR) was used to avoid setting parameters manually in the level of manufacturing process. As the result, It became possible to control parameters of the camera by program. And the cost-down effect was accomplished by improving the reliability of parameter values and reducing the efforts in setting parameters.

• The KIPS Transactions:PartA
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• v.14A no.5
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• pp.301-308
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• 2007

This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.