• Title/Summary/Keyword: Image Processor

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Real-time Stereo Video Generation using Graphics Processing Unit (GPU를 이용한 실시간 양안식 영상 생성 방법)

  • Shin, In-Yong;Ho, Yo-Sung
    • Journal of Broadcast Engineering
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    • v.16 no.4
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    • pp.596-601
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    • 2011
  • In this paper, we propose a fast depth-image-based rendering method to generate a virtual view image in real-time using a graphic processor unit (GPU) for a 3D broadcasting system. Before the transmission, we encode the input 2D+depth video using the H.264 coding standard. At the receiver, we decode the received bitstream and generate a stereo video using a GPU which can compute in parallel. In this paper, we apply a simple and efficient hole filling method to reduce the decoder complexity and reduce hole filling errors. Besides, we design a vertical parallel structure for a forward mapping process to take advantage of the single instruction multiple thread structure of GPU. We also utilize high speed GPU memories to boost the computation speed. As a result, we can generate virtual view images 15 times faster than the case of CPU-based processing.

Analysis of Geometrical and Physical PRoperties of Red Pepper by Machine Vision (기계시각을 이용한 홍고추의 기하학적 및 물리적 특성 분석)

  • 김영복;이승규;김성태;나우정;송대빈;이호준
    • Journal of Biosystems Engineering
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    • v.26 no.3
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    • pp.287-294
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    • 2001
  • The geometrical and physical properties of red peppers were studied for proper design of a red pepper processor. Mass, volume, roundness and compactness of red peppers were calculated from digital images. They were compared with real data and the relations of them were suggested. Roundness of red peppers was ranged from 0.2 to 0.5 and the average value was 0.349. Compactness of red peppers was ranged from 25 to 50 and the average value was 37.1. The regression equations to calculate the volume and mass of red pepper were obtained as y$\_$v/$\_$=/0.553$\varkappa$$_1$+1.441$\varkappa$$_2$-1.013$\varkappa$$_3$(R=0.95) and y$\_$m/=0.252$\varkappa$$_1$+0.938$\varkappa$$_2$-0.499$\varkappa$$_3$-1.5112 (R=0.93), y$\_$v/:volume(㎤), y$\_$m/:mass(g), $\varkappa$$_1$: perimeter(cm), $\varkappa$$_2$: area(㎠), $\varkappa$$_3$: length of major axis(cm), respectively. The direction for aligning the red pepper in a machine processing was easily and perfectly recognized. The response time for digital image processing has to be reduced for more efficient operation. HSI and YIQ values could be useful for recognizing the red pepper from background.

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VLSI Implementation of a Digital Zooming System for Digital Camcorder (디지털 캠코더용 영상확대 시스템의 VLSI 구현)

  • Shin, Jeong-Ho;Jung, Jung-Hoon;Paik, Joon-Ki;Kim, Hyo-Ju
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.9
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    • pp.78-85
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    • 1998
  • In this paper we propose a VLSI implementation technique for camcorder's digital zooming system. The proposed VLSI includes the system clock(CLK), vertical drive(VD), horizontal drive(HD),blank(BLK), and field(FLD) signals as inputs, and produces magnified image as an output, with 256 different magnification ratios. In general, the above mentioned input signals are provided by the CCD driving IC in most camcorders. As a result, the proposed digital zooming VLSI can magnify a part of the input image by up to 256 times, where the magnification ratio can be chosen among 256 different steps. In the application point of view, the proposed VLSI can be used in any digital camcorder for realizing near continuous step digital zooming without any additional circuitry, such as micom or a general purpose digital signal processor.

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3-D Hetero-Integration Technologies for Multifunctional Convergence Systems

  • Lee, Kang-Wook
    • Journal of the Microelectronics and Packaging Society
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    • v.22 no.2
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    • pp.11-19
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    • 2015
  • Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

The Study of Implementation of SignBoard Receiving DARC for Vehicle 1. The Implementation of Sign Board Receiving DARC (차량용 FM 부가방송 수신 전광판의 구현에 관한 연구 1. FM 부가방송 수신 전광판의 구현)

  • 최재석;김영길
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.8
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    • pp.1169-1174
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    • 2002
  • In this paper, we implemented the sign board system that displays user's image, user's sentence, the information from DARC. The existing sign board is displaying only user's image and sentence. Or other existing sign board is displaying the information via CDMA network. However, our system is also able to display the user's message like other system and gain the information more cheap by DARC. This system includes the main processor, the program memory, the external memory, the DARC module and the LED display module. The external memory stores the user's message files and the order file that decides the displaying order of user's file and the DARC information The DARC module extracts the DARC information from FM signal. From the experiment, we could confirm that this system display the DARC information and the user's message by the order file.

Real-Time Object Detection System Based on Background Modeling in Infrared Images (적외선영상에서 배경모델링 기반의 실시간 객체 탐지 시스템)

  • Park, Chang-Han;Lee, Jae-Ik
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.46 no.4
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    • pp.102-110
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    • 2009
  • In this paper, we propose an object detection method for real-time in infrared (IR) images and PowerPC (PPC) and H/W design based on field programmable gate array (FPGA). An open H/W architecture has the advantages, such as easy transplantation of HW and S/W, support of compatibility and scalability for specification of current and previous versions, common module design using standardized design, and convenience of management and maintenance. Proposed background modeling for an open H/W architecture design decreases size of search area to construct a sparse block template of search area in IR images. We also apply to compensate for motion compensation when image moves in previous and current frames of IR sensor. Separation method of background and objects apply to adaptive values through time analysis of pixel intensity. Method of clutter reduction to appear near separated objects applies to median filter. Methods of background modeling, object detection, median filter, labeling, merge in the design embedded system execute in PFC processor. Based on experimental results, proposed method showed real-time object detection through global motion compensation and background modeling in the proposed embedded system.

Enhanced Postprocessing Algorithm for Minutia Extraction Using Various Information in Fingerprint (다양한 지문정보를 이용한 개선된 특징점 추출 후처리 알고리즘)

  • 박태근;정선경
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.3C
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    • pp.359-367
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    • 2004
  • The postprocessing to remove false minutia is important because the extraction of true minutia affects the performance as a key factor in fingerprint identification system. In this paper, we propose an efficient postprocessing algorithm for removing false minutia among the extracted candidates in a thinned image. The proposed algorithm removes false minutia in three steps by using various information in the acquired fingerprint image: the structural information of minutia (end point and bifurcation), the inherent characteristics of fingerprint, and the quality of acquired images. Under Intel Celeron processor environment with 248${\times}$292 images acquired by optic device, the experiments showed that the proposed algorithm efficiently removed false minutia while preserving true minutia. Moreover, the proposed algorithm takes 0.0154 second, which is very small compared to the time for preprocessing (0.343 second).

Semantic Object Detection based on LiDAR Distance-based Clustering Techniques for Lightweight Embedded Processors (경량형 임베디드 프로세서를 위한 라이다 거리 기반 클러스터링 기법을 활용한 의미론적 물체 인식)

  • Jung, Dongkyu;Park, Daejin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.10
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    • pp.1453-1461
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    • 2022
  • The accuracy of peripheral object recognition algorithms using 3D data sensors such as LiDAR in autonomous vehicles has been increasing through many studies, but this requires high performance hardware and complex structures. This object recognition algorithm acts as a large load on the main processor of an autonomous vehicle that requires performing and managing many processors while driving. To reduce this load and simultaneously exploit the advantages of 3D sensor data, we propose 2D data-based recognition using the ROI generated by extracting physical properties from 3D sensor data. In the environment where the brightness value was reduced by 50% in the basic image, it showed 5.3% higher accuracy and 28.57% lower performance time than the existing 2D-based model. Instead of having a 2.46 percent lower accuracy than the 3D-based model in the base image, it has a 6.25 percent reduction in performance time.

Optical Lining Device Development of PDP and FED Vacuum Binding (PDP, FED의 진공접합용 광학정렬장치 개발)

  • Lee, Jeung Young;Kim, Dae Nyoun;Kim, Kyung Chan
    • Journal of Korean Ophthalmic Optics Society
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    • v.7 no.2
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    • pp.123-128
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    • 2002
  • This study is to develop optical lining device for vacuum binding of PDP and FED. It is very difficult precise technology to line a front board and back board accurately and fast every time when two boards are joined together. Especially, these technology is difficult to be transferred from developed countries. In this study, the accuracy of lining of two boards in vacuum device by developing an optical lining device for vacuum binding as an image processor and CCD camera configured to be high magnification lens with long focus using optical design.

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A VLSI Architecture of an 8$\times$8 OICT for HDTV Application (HDTU용 8$\times$8 최적화 정수형 여현 변환의 VLSE 구조)

  • 송인준;황상문;이종하;류기수;곽훈성
    • Journal of the Korean Institute of Telematics and Electronics T
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    • v.36T no.1
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    • pp.1-7
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    • 1999
  • We present VLSI architecture for a high performance 2-D DCT processor which is used compressing system of real time image processing or HDTV using fast computational algorithm of the Optimized Integer Cosine Transform(OICT). The coefficients of the OICT are integer, so the OICT performs only the integer operations for both forward and inverse transform. Therefore the proposed architecture could be greatly enhanced in improving the speed, reduced the hardware cost considerably by replacing the multiplication operations with shift and addition operations compared with DCT which performs floating-point operations.

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