• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.7 s.361
• /
• pp.62-70
• /
• 2007

In this paper, we design a mobile camera processor to support the MIPI CSI-2 and DPHY specification. The lane management sub-layer of CIS2 handles multi-lane configuration. Thus conceptually, the transmitter and receiver have each independent buffer on multi lanes. In the proposed architecture, the independent buffers are merged into a single common buffer. The single buffer architecture can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. For a key issue for the data synchronization problem, the synchronization start codes are added as the starting for image data. We design synchronization logic to synchronize the received clock and to generate the byte clock. We present the verification results under proposed test bench. And we show the waves of simulation and logic synthesis results of the designed processor.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.37 no.2
• /
• pp.50-59
• /
• 2000

Stereo vision is a technique extracting depth information from stereo images, which are two images that view an object or a scene from different locations. The most important procedure in stereo vision, which is called stereo matching, is to find the same points in stereo images. It is difficult to match stereo images in real time because stereo matching requires heavy calculation. In this Paper we design a digital VLSI to Process stereo matching in real time, which we call stereo image match processor (SIMP). For implementation of real time stereo matching, sliding memory and minimum selection tree are presented. SIMP is designed with pipeline architecture and parallel processing. SIMP takes 64 gray level 64$\times$64 stereo images and yields 8 level 64 $\times$64 disparity map by 3 bit disparity and 12 bit address outputs. SIMP can process stereo images with process speed of 240 frames/sec.

• Journal of The Korean Astronomical Society
• /
• v.47 no.2
• /
• pp.43-47
• /
• 2014

Many advanced ground-based solar telescopes improve the spatial resolution of observation images using an adaptive optics (AO) system. As any AO correction remains only partial, it is necessary to use post-processing image reconstruction techniques such as speckle masking or shift-and-add (SAA) to reconstruct a high-spatial-resolution image from atmospherically degraded solar images. In the New Vacuum Solar Telescope (NVST), the spatial resolution in solar images is improved by frame selection and SAA. In order to overcome the burden of massive speckle data processing, we investigate the possibility of using the speckle reconstruction program in a real-time application at the telescope site. The code has been written in the C programming language and optimized for parallel processing in a multi-processor environment. We analyze the scalability of the code to identify possible bottlenecks, and we conclude that the presented code is capable of being run in real-time reconstruction applications at NVST and future large aperture solar telescopes if care is taken that the multi-processor environment has low latencies between the computation nodes.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.39 no.3
• /
• pp.66-77
• /
• 2002

This paper deals with an implementation of the navigation parameter extraction technique using the TMS320C80 multimedia video processor (MVP). Especially, this Paper focuses on the relative position estimation algorithm which plays an important role in real-time operation of the overall system. Based on the relative position estimation algorithm using the images obtained at two locations, we develop a fast algorithm that can reduce large amount of computation time and fit into fixed-point processors. Then, the algorithm is reconfigured for parallel processing using the 4 parallel processors in the MVP. As a result, we shall demonstrate that the navigation parameter extraction system employing the MVP can operate at full-frame rate, satisfying real-time requirement of the overall system.

• Journal of the Institute of Convergence Signal Processing
• /
• v.12 no.1
• /
• pp.13-19
• /
• 2011

In this paper, a visual surveillance system using SOPC based NIOS II embedded processor and C2H compiler was implemented. In this system, the IP is constructed by C2H compiler for the output of the camera images, image processing, serial communication and network communication, then, it is implemented to effectively control each IP based on the SOPC and the NIOS II embedded processor. And, an algorithm which updates the background images for high speed and robust detection of the moving objects is proposed using the Adaptive Gaussian Mixture Model(AGMM). In results, it can detecte the moving objects(pedestrians and vehicles) under day-time and night-time. It is confirmed that the proposed AGMM algorithm has better performance than the Adaptive Threshold Method(ATM) and the Gaussian Mixture Model(GMM) from our experiments.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.1 no.2
• /
• pp.27-31
• /
• 2000

Thermal imaging system is implemented for the measurement and the analysis of the thermal distribution of the target objects. The main Part of the system is thermal camera in which a focal plane array typed sensor is introduced The sensor detects mid-range infrared spectrum or target objects and then it output generic video signal which should be processed to form a thermal image frame. A digital signal processor(DSP) in the system inputs analog to digital converted data. performs algorithms to improve the thermal images and then outputs the corrected frame data to frame buffers for NTSC encoding and for digital outputs.. To enhance the quality of the thermal images, two point correction method is applied. Figures indicate that the corrected thermal images are much improved.

• Journal of Institute of Control, Robotics and Systems
• /
• v.11 no.1
• /
• pp.84-91
• /
• 2005

In this paper, we describe the real-time parallel processing simulator developed for the use of performance analysis of rolling missiles. The real-time parallel processing simulator developed here consists of seeker emulator generating infrared image signal on aircraft, real-time computer, host computer, system unit, and actual equipments such as auto-pilot processor and seeker processor. Software is developed from mathematic models, 6 degree-of-freedom module, aerodynamic module which are resided in real-time computer, and graphic user interface program resided in host computer. The real-time computer consists of six TIC-40 processors connected in parallel. The seeker emulator is designed by using analog circuits coupled with mechanical equipments. The system unit provides interface function to match impedance between the components and processes very small electrical signals. Also real launch unit of missiles is interfaced to simulator through system unit. In order to apply the real-time parallel processing simulator to performance analysis equipment of rolling missiles it is essential to perform the performance verification test of simulator.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.3
• /
• pp.17-25
• /
• 1999

This paper proposes a new bit-serial multiplier/divider architecture to reduce the hardware complexity significantly and to maintain the same number of cycles compared with existing architectures. Since the proposed bit-serial multiplier/divider architecture does not extend the number of bits in registers and an adde $r_tractor to calculate a partial product or a partial remainder, the hardware overhead can be greatly reduced. In addition, the proposed architecture can perform an additio $n_traction and a shift operation in parallel and the number of cycles for $\textit{N}$-bit multiplication and division for the proposed circuits is $\textit{N}$ and $\textit{N}$ + 2, repectively. Thus, the number of cycles for multiplication and division is the same compared with existing architectures. The SliM Image Processor employs the proposed multiplier/divider architecture and proves the performance of the proposed architecture.cture.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.10a
• /
• pp.416-419
• /
• 2003

The cellular neural networks have the circuit structure that differs from the form of general neural network. It consists of an array of the same cell which is a simple processing element, and each of the cells has local connectivity and space invariant template property. In this paper, time-multiplex image processing technique is applied for processing large images using small size CNN cell block, and we simulate the edge detection of a large image using the simulator implemented with a c program and matlab model. A 5$\times$5 CNN hardware and pre post processor is also implemented and is under test.

• The Transactions of the Korea Information Processing Society
• /
• v.5 no.5
• /
• pp.1367-1376
• /
• 1998

In this paper we propose an real time marker detection algorithm for motion analysis both in 2 dimensions and 3 dimensions with CCD camera and rfame grabber only which has no image processor. The main algorithm consists of the following 3 algorithms; 1) the tracing algorithm that makes it possible to predict the expected marker location by narrowing the searching boundary, 2) the searching algorithm that detects the marker in the expected boundary using Ad-hoc previous screen search technique, tornado search method rotate diagonal search method search technique, 3) the algorithm that finds the central point of the detected marker. We try to narrow the searching boundary for real time processing. Also, it is able to find the central point of the detected marker much faster than typical contour tracing algorithm.