• Journal of Korean Society of Transportation
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• v.12 no.1
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• pp.97-116
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• 1994

Today advanced traffic management systems are required because of a high increase in traffic demand. Accordingly, the objective of this study is to take advantage of image processing systems and present image processing methods available for collection of the data on traffic characteristics, and then to investigate the possibility of traffic flow analysis by means of comparison and analysis of measured traffic flow. Data were collected at two places of Daegu city and Kyongbu expressway by using VTR. Rear view (down stream) and frontal view (up stream) methods were employed to compare and analyze traffic characteristics including traffic volume, speed, time-headway, time-occupancy, and vehicle-length, by analysis of measured traffic flow and image processing respectively. Judging from the results obtained by this study, image processing techniques are sufficient for the analysis of traffic volume, but a frame grabber equipped with high speed processor is necessary as well, with low level system judged to be sufficient for traffic volume analysis.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10b
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• pp.822-825
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• 1988

In this paper, we present a system which enables a real-time measurement of the number and also the body length of the fry (baby fish) using a line image sensor. Here, we consider a situation that fry are transported from a pond to another, pond through a pipe. At one position of the pipe a transparent rectanglar channel is mounted. The images of the fry, which run through this rectanglar channel, are detected by a line image sensor. The image signals are digitized to binary ones and the contour of the fry are detected. After that, a real-time image analysis is executed with a digital signal processor. Labeling program analyses the connection of every pixel. The results are transfered to a personal computer and displayed on the online monitor graphically.

• Journal of Institute of Control, Robotics and Systems
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• v.18 no.5
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• pp.479-486
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• 2012

In this paper, a ranging system is proposed that is able to measure 360 degree omnidirectional distances to environment objects. The ranging system is based on the structured light imaging system with catadioptric omnidirectional mirror. In order to make the ranging system robust against environmental illumination, efficient structured light image processing algorithms are developed; sequential integration of difference images with modulated structured light and radial search based on Bresenham line drawing algorithm. A dedicated FPGA image processor is developed to speed up the overall image processing. Also the distance equation is derived in the omnidirectional imaging system with a hyperbolic mirror. It is expected that the omnidirectional ranging system is useful for mapping and localization of mobile robot. Experiments are carried out to verify the performance of the proposed ranging system.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.224-227
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• 1999

This paper presents a design of the real-time preprocessor for CMOS image sensor suitable to the digital camera applications. CMOS image sensor offers some advantages in on-chip integration, system power reduction, and low cost. However, it has a lower-quality image than CCDs. We describe an image enhancement algorithm, which includes color interpolation, color correction, gamma correction, sharpening, and automatic exposure control, to compensate for this disadvantage, and present its efficient hardware architecture to implement on the real-time processor. The presented real-time preprocessor was designed using VHDL, and it contains about 19.2K logic gates. We also implement our system on FPGA chips in order to provide the real-time adjustment and it was successfully tested.

• Proceedings of the KOSOMBE Conference
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• v.1992 no.11
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• pp.105-108
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• 1992

In this paper, we have implemented the telemedicine system which has a color image system and a biosignal processor. The inputted image is acquisited to 512 by 480 color image data. The col looted data is compressed to 1/5 of the original image data by using 1/5 and compression algorithm. A biological signals are inputted by 12 bit A/D converter into the system. In case of using 2400bps modem, a frame full color image data and biological information data needed 10 minutes in transmission.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.18 no.35
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• pp.1-8
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• 1995

Automatic inspection system software for display image characteristic of CRT is developed. There are two major contributions of this software development. One is that the data from measuring equipments which was usually collected manually is automatically collected through RS-232C port and is saved in computer, then, trend analysis graph and final reports are generated. The other is that evauation of characteristic of electron gun was automatically processed by CCD camera and image processing technique. The system is developed under MS-Windows environment utilizing Borland C++4.0 Compiler and DT 3852-8 image processor board. This system can save the time and man power to measure and to anayze the image characteristics relative to current method.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.484-487
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• 1987

In order to measure object larger than the optical field-of-view most video measurement systems utilize some sort of precision staging mechanism, and to utilize such a staging systems, Auto-Measurement System implemented in this paper has a precision of its own which affect the overall repeatability of the measuring instrument.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1433-1443
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• 1993

DCT(Discrete Cosine Transform) / IDCT(Inverse DCT) is widely used in various image compression and decompression systems as well as in DSP(Digital Signal Processing) applications. Since DCT/ IDCT is one of the most complicated part of the compression system, the performance of the system can be greatly enchanced by improving the speed of DCT/IDCT operation. In this thesis, we designed a DCT/IDCT core processor using module generator technique. By utilizing the partial sum and DA(Distributed Arithmetic) techniques, the DCT/ IDCT core processor is designed within small area. It is also designed to perform the IDCT(Inverse DCT) operation with little additional circuitry. The pipeline structure of the core processor enables the high performance, and the high accuracy of the DCT/IDCT operation is obtained by having fewer rounding stages. The proposed design is independent of design rules, and the number of the input bits and the accuracy of the internal calculation coa be easily adjusted due to the module generator technique. The accuracy of the processor satisfies the specifications in CCITT recommendation H, 261.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.11-21
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• 2011

This paper introduces an SIMD(Single Instruction Multiple Data) based parallel processor that efficiently processes massive data inherent in multimedia. In addition, this paper implements MMX(MultiMedia eXtension)-type instructions on the data parallel processor and evaluates and analyzes the performance of the MMX-type instructions. The reference data parallel processor consists of 16 processors each of which has a 32-bit datapath. Experimental results for a JPEG compression application with a 1280x1024 pixel image indicate that MMX-type instructions achieves a 50% performance improvement over the baseline instructions on the same data parallel architecture. In addition, MMX-type instructions achieves 100% and 51% improvements over the baseline instructions in energy efficiency and area efficiency, respectively. These results demonstrate that multimedia specific instructions including MMX-type have potentials for widely used many-core GPU(Graphics Processing Unit) and any types of parallel processors.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.36-44
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• 2015

This paper proposes a low-complexity processor to correct vignetting and barrel distortion for wide-angle cameras. The proposed processor calculates the required correcting factors by employing the piecewise linear approximation so that the hardware complexity can be reduced significantly while maintaining correction quality. In addition, the processor is designed to correct the two distortions concurrently in a singular pipeline, which reduces the overall complexity. The proposed processor is implemented with 18.6K logic gates in a $0.11{\mu}m$ CMOS process and shows the maximum correction speed of 200Mpixels/s for correcting an image of which size is $2048{\times}2048$.