• 센서학회지
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• 제24권5호
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• pp.299-305
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• 2015

Since the natural disasters such as floods, droughts, heat wave and cold wave are increasing, the need for risk management is necessary to minimize the damage with utilizing IT technology. Also, the monitoring services of disaster response type have been developed and applied. Recently, the open source hardware based on the signal of the sensor, or the monitoring studies have been carried. In this paper, by analyzing a low-cost open source hardware platform such as Beagle board, we examine the utilization of the hardware-based module for sensor monitoring.

• Journal of Power Electronics
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• 제6권2호
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• pp.114-120
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• 2006

This paper compares two types of direct torque controllers for permanent magnet synchronous motors(PMSMs). These controllers both use a single-chip FPGA(Field Programmable Gate Array) but have differing hardware configurations. One of the controllers was constructed by programming a soft-core CPU and hardware logic circuits written in VHDL(Very high speed IC Hardware Description Language), while the other was constructed of only hardware logic circuits. The characteristics of these two controllers were compared in this paper. The results show the controller constructed of only hardware logic circuits was able to shorten the control period and it was able to suppress the low torque ripple.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2009년도 추계학술발표대회
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• pp.67-68
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• 2009

Increasing use of embedded systems has made many improvements on hardware development for specific purpose. Hardware changes are more expensive and harder to implement rather than software changes. Developers need tools to do design and testing of new hardware. Many simulation tools have been made to mimic the hardware and allow developer to test programs on top of new hardware. Virtual Development Environment for Embedded Software (VDEES) is one of the alternatives available. It provides an open source based platform and an Integrated Development Environment (IDE) that can be used to build and testing newly made component, faster and at low-cost.

• 한국정보통신학회논문지
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• 제23권12호
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• pp.1609-1617
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• 2019

ECC (Elliptic Curve Cryptography)와 RSA를 기반으로 하는 다양한 공개키 암호 프로토콜 구현을 지원하는 하드웨어 가속기 설계에 관해 기술한다. NIST 표준으로 정의된 소수체 상의 5가지 타원곡선과 3가지 키길이의 RSA를 지원하며 또한, 4가지 타원곡선 점 연산과 6가지 모듈러 연산을 지원하도록 설계되어 ECC와 RSA 기반 다양한 공개키 암호 프로토콜의 하드웨어 구현에 응용될 수 있다. 저면적 구현을 위해 내부 유한체 연산회로는 32 비트의 데이터 패스로 설계되었으며, 워드 기반 몽고메리 곱셈 알고리듬, 타원곡선 점 연산을 위해서는 자코비안 좌표계, 그리고 모듈러 곱의 역원 연산을 위해서는 페르마 소정리를 적용하였다. 설계된 하드웨어 가속기를 FPGA 디바이스에 구현하여 EC-DH 키교환 프로토콜과 RSA 암호·복호 둥작을 구현하여 하드웨어 동작을 검증하였다. 180-nm CMOS 표준 셀 라이브러리로 합성한 결과, 50 MHz 클록 주파수에서 20,800 등가게이트와 28 kbit의 RAM으로 구현되었으며, Virtex-5 FPGA 디바이스에서 1,503 슬라이스와 2개의 BRAM으로 구현되었다.

• 정보과학회 논문지
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• 제44권4호
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• pp.344-351
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• 2017

속성 기반 서명은 속성을 가지는 서명키를 사용하여 속성 술어를 기반으로 하는 서명을 생성하는 암호 방식이다. 속성 기반 서명에서 서명을 생성하는 동안 서명키가 유출된다면, 해당 서명키에 대한 서명이 위조될 수 있는 문제가 발생한다. 따라서 서명 생성은 보안이 보장되는 하드웨어에서 수행되어야 한다. 이러한 하드웨어를 보안 하드웨어라고 명명한다. 그러나 보안 하드웨어는 연산속도가 느리기 때문에 속성 기반 서명과 같은 많은 연산을 빠른 시간 안에 수행하기에는 적합하지 않다. 이 논문은 속성 기반 서명의 연산을 분리하여 성능이 좋은 일반 하드웨어와 보안 하드웨어로 이루어지는 시스템에서 효율적으로 사용가능한 속성 기반 서명 기법을 제안한다. 제안하는 기법은 기존에 존재하는 임의의 속성 기반 서명과 일반 전자서명으로 설계가 가능하며, 속성 기반 서명이 안전하지 않은 환경에서 수행되더라도 일반 전자서명을 보안 하드웨어에서 수행함으로써 안전성을 보장한다. 제안된 논문은 기존의 속성 기반 서명을 보안 하드웨어에서 생성하는 것에 비해서 11배의 성능향상을 보인다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2011년도 춘계학술대회
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• pp.643-645
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• 2011

We analysed a hardware design issues, which is strong, compact and efficient. Due to its low area constraints, primitive based on hardware is especially suited for RFID (Radio Frequency Identification) devices. primitive is based on the classical DES (Data Encryption Standard) design. This approach makes it possible to considerably decrease chip size requirements.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.131.1-131
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• 2001

At the present time, multimedia chip, internet application, and network equipment is designed by using ARM core. Because it has a good debugging, software compiler and needed low power. We must process a data coding to send a multimedia data by real time. So need to connect software and hardware algorithm. In this research, We design interface for ARM9/AMBA based board using VHDL for these function implementation. The board is used the ARM company´s ARM940T for software function implementation and Xilinx company´s Virtex E2000 for hardware function algorithm. The various hardware algorithm (ME,ME,DCT) block for performance can be implemented on this system.

• 전자공학회논문지B
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• 제31B권4호
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• pp.123-128
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• 1994

Hardware realization of a digital 2-D homomorphic filter for real time contrast enhancement of video signal is presented. In homomorphic filter, logarithmic and exponential conversion used the memory lookup table method and because the hardware is implemented by multiplierless TTL devices, it can be designed to specific IC. The contrast gain can be controlled externally and the transfer function of homomorphic filter can be easily varied by the change of lookup table memory data.

• 전기학회논문지
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• 제64권11호
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• pp.1564-1570
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• 2015

This paper intends to suggest a sensing circuit of PWM voltage for a motor emulator operated in the inverter. In the emulation of the motor using a power converter, it is necessary to measure instantaneous voltage at the PWM voltage loaded from the inverter. Using a filter can generate instantaneous voltage, while it is difficult to follow the rapidly changing inverter voltage caused by the propagation delay and signal attenuation. The method of measuring the duty of PWM using FPGA can generate output voltage from the one-cycle delay of PWM, while the cost of hardware is increasing in order to acquire high precision. This paper suggests a PWM voltage sensing circuit using the analogue system that shows high precision, one-cycle delay of PWM and low-cost hardware. The PWM voltage sensing circuit works in the process of integrating input voltage for valid time by comparing levels of three-phase PWM input voltage, and produce the output value integrated at zero vector. As a result of PSIM simulation and the experiment with the produced hardware, it was verified that the suggested circuit in this paper is valid.

• KEPCO Journal on Electric Power and Energy
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• 제7권1호
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• pp.101-105
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• 2021

Encouragement of DER from Korean government with several policies boosts DER installation in power system. When the penetration of DER in the grid is getting high, loss of generation with break-away of DER by abnormal grid conditions should be considered, because loss of high generation causes abnormal low frequency and additional operations of protection system. Therefore, KEPCO where is Korean power utility is preparing improvement in regulations for DERs connected to the grid to support abnormal grid conditions such as low and high frequencies or voltages. This is called 'Ride Through' because the requirement is for DER to maintain grid connection during required periods when abnormal grid conditions occur. However, it is not easy to have a test for ride through capability in reality because emulation of abnormal grid conditions is not possible in real power system in operation. Also, it is not easy to have a study on grid effect when ride through capability fails with the same reason. PHILs (Power Hardware In the Loop System) makes it possible to analyze power system and hardware performance at once. Therefore, this paper introduces PHILs test methods and presents verification of ride through capability especially for low voltage grid conditions.