• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.60-67
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• 2013

Test cost reduction is necessary to test a complex System-on-a-Chip(SoC) which adopts various Intellectual Properties (IP). In this paper, test architecture with low pin count which is able to IP-based SoC test, using IEEE Std. 1149.7 and IEEE Std. 1500, is proposed. IEEE Std. 1500 provides independent access mechanism for each IP in IP-based SoC test. In this paper, just two test pins are required by composing that these independent access mechanism can be controlled by IEEE Std. 1149.7. The number of Chips which are tested at the same time is increased by reducing required test pin count at wafer and package level test, and consequently the overall manufacturing test cost will be reduced significantly.

• Journal of the Korea Society of Computer and Information
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• v.13 no.2
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• pp.221-233
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• 2008

In general, we use a Parallel processing computer manufactured specially for the purpose of parallel processing to do high performance computings. But we can depoly and use a PC cluster composed of several common PCs instead of the very expensive parallel processing computer. A common way to get a PC cluster is to adopt the star topology network connected by a switch hub. But in this paper, we grope efficient implementations of hypercube networks based on TCP/IP to connect 8 PCs directly for more useful parallel processing environment, and make evaluations on functionality and efficiency of them using ping, netperf, MPICH. The two proposed methods of implementation are IP configuration based on link and IP configuration based on node. The results of comparison between them show that there is not obvious difference in performance but the latter is more efficient in simplicity of routing table. For verification of functionality, we compare the parallel processing results of an application in them with the same in a star network based PC cluster. These results also show that the proposed hypercube networks support a perfect parallel processing environment respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.26-33
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• 2005

Exact prediction of resource demands for future calls enhances the efficiency of the limited resource utilization in resource reservation methods for potential calls in wireless IP networks. In this paper, we propose a LMS-Wiener resource(bandwidth) prediction for future handoff calls, and then an the proposed method is compared with an existing Wiener-based method in terms of prediction error through our simulations. In our simulations, we assume that handoff call arrivals follow a non-Poisson process and each handoff call has an non-exponentially distributed channel holdingtime in the cell, considering that handoff call arrival pattern is not Poisson distribution but non-Poisson for long periods of time in wireless picocellular IP networks. Simulation results show that the prediction error in the proposed method converges to the lower value while in an existing method increase as time is passed. Therefore we may conclude that the proposed method improves the efficiency of resource utilization by more exactly predicting resource demands for future handoff calls than an existing method.

• Geophysics and Geophysical Exploration
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• v.24 no.4
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• pp.149-157
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• 2021

Given that induced polarization (IP) and direct current (DC) resistivity surveys are similar in terms of data acquisition, most DC resistivity systems are equipped with a time-domain IP data acquisition function. In addition, the time-domain IP data include the DC resistivity values. As such, IP and DC resistivity data are intimately linked, and the inversion of IP data is a two-step process based on DC resistivity inversions. Nevertheless, IP surveys are rarely applied, in contrast to DC resistivity surveys, as proper inversion software is unavailable. In this study, through numerical modeling and inversion experiments, we analyze the problems with the conventional inverse mapping technique used to invert time-domain IP data. Furthermore, we propose a modified inverse mapping technique that can effectively suppress inversion artifacts. The performance of the technique is confirmed through inversions applied to synthetic IP data.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Progress in Medical Physics
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• v.18 no.2
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• pp.55-64
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• 2007

Our objective was to evaluate the clinical feasibility of spatial domain filtering as an alternative to additional image reconstruction using different kernels in CT. Kernels were grouped as H30 (head medium smooth), B30 (body medium smooth), S80 (special) and U95 (ultra sharp). Derived from thin coilimated source images, four sets of images were generated using phantom kernels. MTF (50%, 10%, 2%) measured with H30 (3.25, 5.68, 7.45 Ip/cm) B30 (3.84, 6.25, 7.72 Ip/cm), S80 (4.69, 9.49, 12.34 Ip/cm), and U95 (14.19, 20.31, 24.67 Ip/cm). Spatial resolution for the U95 kernel (0.6 mm) was 33.3% greater than that of the H30 and B30 (0.8 mm) kernels. Initially scanned kernels images were rated for subjective image qualify, using a five-point scale. Image scanned with a convolution kernel led to an increase in noise (U95), whereas the results for CT attenuation coefficient were comparable. CT images increase the diagnostic accuracy in head (H30), abdomen (B30), temporal bone and lung (U95) kernels may be controlled by adjusting CT various algorithms, which should be adjusted to take into account the kernels of the CT undergoing the examination.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.113-124
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• 2009

With increasing multicore system, much effort has been put on the performance improvement of its application. Because multicore system has multiple processing devices in one system, its processing power increases compared to the single core system. However in many cases the advantages of multicore can not be exploited fully because the existing software and hardware were designed to be suitable for single core. When the existing software runs on multicore, its performance improvement is limited by the bottleneck of sharing resources and the inefficient use of cache memory on multicore. Therefore, according as the number of core increases, it doesn't show performance improvement and shows performance drop in the worst case. In this paper we propose a method of performance improvement of multicore system by applying Flow-Level Parallelism to the existing TCP/IP network application and operating system. The proposed method sets up the execution environment so that each core unit operates independently as much as possible in network application, TCP/IP stack on operating system, device driver, and network interface. Moreover it distributes network traffics to each core unit through L2 switch. The proposed method allows to minimize the sharing of application data, data structure, socket, device driver, and network interface between each core. Also it allows to minimize the competition among cores to take resources and increase the hit ratio of cache. We implemented the proposed methods with 8 core system and performed experiment. Experimental results show that network access speed and bandwidth increase linearly according to the number of core.

• TTA Journal
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• s.73
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• pp.116-122
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• 2001

현재 3G 기술의 주된 진전은 IP기반은 프로토콜을 기반으로 하는 핵심망의 부분이라고 해도 과언이 아니다. 30GPP2의 경우, IETF의 Mobile IP를 호스트의 매끄러운 로밍을 위한 핵심망의 라우팅 프로토콜로 채택하고 있으며 3GPP 역시 기존의 GTP기반의 GPRS 망에서 인터넷과의 글로벌한 로밍을 위해 IETF의 Mobile IP를 채택하려고 하는 입장이다. 본 글은 3G 기술, 특히 핵심망에서 호스트의 매끄러운 로밍을 지원하기 위한 기술지원 동향을 ITU의 입장이 아닌 IETF의 입장에서 고찰하도록 한다. 이를 위해 본 글은 IETF에서 3G 셀룰러망을 위한 표준규격 워킹그룹을 분류하고 각 워킹그룹의 역할을 고찰해 보도록 한다.

• Review of KIISC
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• v.8 no.2
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• pp.5-17
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• 1998

본 고에서는 초고속정보통신망의 기반구조가 될 ATM 및IP/ATM에서의 보호체계 및 인터넷기반인 IP에서의 보호체계에 관하여 기술한다. IPv6에서는 보호서비스를 제공하기 위하여 인증 헤드와 ESP를 사용하고 있으며 이러한 인증 헤드와 ESP에서의 보호서비스 제공에 관하여 기술한다. ATM에서의 보호체계는 ATM포험에서 지금까지 연구한 ATM보안 규격 내용을 보호서비스 측면에서 소개한다. 또한 IP/ATM의 특성을 고려하여 IP/ATM에 적합한 보호서비스와 보호기술들을 기술한다.

• Information and Communications Magazine
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• v.26 no.2
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• pp.38-43
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• 2009

SIP는 세션 제어 프로토콜로 IP 기반의 음성, 멀티미디어 데이터 전송 제어뿐만 아니라 차세대 네트워크에서 통합 어플리케이션 세션 제어를 위한 핵심 프로토콜이다. 이를 이용한 SIP 이동성 제어 기술은 Mobile IP 기반 네트워크 레벨의 프로토콜과 함께 차세대 이동성 제어를 위한 기술로 주목된다. 본 고에서는 All-IP 환경에서 SIP프로토콜을 이용한 이동성 제어 기술을 알아보고, 이종 액세스 망 환경에서 망의 특징 및 요구사항에 따른 SIP 이동성 제어 기법을 소개한다.