• Title/Summary/Keyword: IP core

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Advanced Path-Migration Mechanism for Enhancing Signaling Efficiency in IP Multimedia Subsystem

  • Chang, Kai-Di;Chen, Chi-Yuan;Hsu, Shih-Wen;Chao, Han-Chieh;Chen, Jiann-Liang
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.6 no.1
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    • pp.305-321
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    • 2012
  • Since Internet Protocol (IP) is the most important protocol in Next Generation Networks (NGNs), 3rd Generation Partnership Project (3GPP) utilizes Session Initial Protocol (SIP) based on IP as the base protocol for negotiating sessions in IP Multimedia Subsystem (IMS). Different from traditional circuit-switched network, in IMS, the media traffic and signaling are delivered through IP transport. The media traffic may affect the signaling efficiency in core network, due to traffic collisions and best effort packets delivery. This paper proposes a novel path-migration mechanism for enhancing the traffic efficiency in integrated NGN-IMS. The simulation results show that the interference and traffic collision can be reduce by applying proposed path-migration mechanism and the signaling efficiency in core network can be improved with higher system capability and voice quality.

Design and Implementation MoIP Wall-pad platform using ARM11 (ARM11 을 이용한 MoIP 월패드 플랫폼 구현)

  • Jung, Yong-Kuk;Kim, Dae-Sung;Heo, Kwang-Seon;Kweon, Min-Su;Choi, Young-Gyu
    • Annual Conference of KIPS
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    • 2011.04a
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    • pp.46-49
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    • 2011
  • This paper is to implement MoIP platform to send and receive video and audio at the same time by using high-performance Dual Core Processor. Even if Wall-Pad key component of a home network system is released by using embedded processors, it's lacking of performance in terms of multimedia processing and feature of video telephony through which video and voice are exchanged simultaneously. The main reason could be that embedded processors currently being used do not provide enough performance to support both MoIP call features and various home network features simultaneously. In order to solve these problems, Dual processor could be used, but in the other hands it brings another disadvantage of high cost. Therefore, this study is to solve the home automation features and video telephony features by using Dual Core Processor based on ARM 11 Processor and implement the MoIP Wall-Pad which can reduce the board design costs and component costs, and improve performance. The platform designed and implemented in this paper verified performance of MoIP to exchange the video and voice at the same time under the situation of Ethernet network.

A OSPF Routing Scheme based on Energy Profiles and Its Characteristics for QoS-Aware Energy Saving(QAES) in IP Core Networks (IP 네트워크에서 QoS-Aware Energy Saving(QAES)을 위한 Energy Profile 기반 OSPF 라우팅 방식 및 특성)

  • Seo, Yusik;Han, Chimoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.1
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    • pp.9-21
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    • 2016
  • Nowadays various methods for energy saving have been studied in IP networks. This paper suggests a 2-phase OSPF routing method for energy saving on IP networks having various energy profiles and analyzes its characteristics. The phase-1 of the routing is an OSPF routing method considering the energy cost of devices besides existing metrics to minimize energy consumption. In the phase-2 of the routing, it makes core nodes go into sleep sate for energy saving and reroutes the paths affected by sleeping core nodes. At this time, we confirm that the characteristics of mean delay and energy efficiency can be satisfied by limiting an allowable hop number in the reroute paths, and utilization rate of nodes and links for assuring energy saving and network-level QoS. Since the efficiency of energy saving and delay characteristics differ according to selection methods of core nodes to go into sleep state, it is that the a method of core node selection based on MP(minimum_path) is more excellent than others in terms of network-level QoS and energy saving in IP networks.

Low-latency SAO Architecture and its SIMD Optimization for HEVC Decoder

  • Kim, Yong-Hwan;Kim, Dong-Hyeok;Yi, Joo-Young;Kim, Je-Woo
    • IEIE Transactions on Smart Processing and Computing
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    • v.3 no.1
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    • pp.1-9
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    • 2014
  • This paper proposes a low-latency Sample Adaptive Offset filter (SAO) architecture and its Single Instruction Multiple Data (SIMD) optimization scheme to achieve fast High Efficiency Video Coding (HEVC) decoding in a multi-core environment. According to the HEVC standard and its Test Model (HM), SAO operation is performed only at the picture level. Most realtime decoders, however, execute their sub-modules on a Coding Tree Unit (CTU) basis to reduce the latency and memory bandwidth. The proposed low-latency SAO architecture has the following advantages over picture-based SAO: 1) significantly less memory requirements, and 2) low-latency property enabling efficient pipelined multi-core decoding. In addition, SIMD optimization of SAO filtering can reduce the SAO filtering time significantly. The simulation results showed that the proposed low-latency SAO architecture with significantly less memory usage, produces a similar decoding time as a picture-based SAO in single-core decoding. Furthermore, the SIMD optimization scheme reduces the SAO filtering time by approximately 509% and increases the total decoding speed by approximately 7% compared to the existing look-up table approach of HM.

An Efficient Secrete Key Protection Technique of Scan-designed AES Core (스캔 설계된 AES 코아의 효과적인 비밀 키 보호 기술)

  • Song, Jae-Hoon;Jung, Tae-Jin;Jeong, Hye-Ran;Kim, Hwa-Young;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.2
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    • pp.77-86
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    • 2010
  • This paper presents an efficient secure scan design technique which is based on a fake key and IEEE 1149.1 instruction to protect secret key from scan-based side channel attack for an Advanced Encryption Standard (AES) core embedded on an System-on-a-Chip (SoC). Our proposed secure scan design technique can be applied to crypto IP core which is optimized for applications without the IP core modification. The IEEE 1149.1 standard is kept, and low area, low power consumption, very robust secret-key protection and high fault coverage can be achieved compared to the existing methods.

Energy Saving Characteristics on Burst Packet Configuration Method using Adaptive Inverse-function Buffering Interval in IP Core Networks (IP 네트워크에서 적응적 역함수 버퍼링 구간을 적용한 버스트패킷 구성 방식에서 에너지 절약 특성)

  • Han, Chimoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.8
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    • pp.19-27
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    • 2016
  • Nowadays the adaptive buffering techniques for burst stream packet configuration and its operation algorithm to save energy in IP core network have been studied. This paper explains the selection method of packet buffering interval for energy saving when configuring burst stream packet at the ingress router in IP core network. Especially the adaptive buffering interval and its implementation scheme are required to improve the energy saving efficiency at the input part of the ingress router. In this paper, we propose the best adaptive buffering scheme that a current buffering interval is adaptively buffering scheme based on the input traffic of the past buffering interval, and analyze its characteristics of energy saving and end-to-end delay by computer simulation. We show the improvement of energy saving effect and reduction of mean delay variation when using an appropriate inverse-function selecting the buffering interval for the configuration of burst stream packet in this paper. We confirm this method have superior properties compared to other method. The proposed method shows that it is less sensitive to the various input traffic type of ingress router and a practical method.

Prioritizing Core Subjects in ISO 26000 for Achieving Corporate Social Responsibility (기업의 사회적 책임경영 구현을 위한 중점 추진요소)

  • Kim, Yun-Tai;Riew, Moon-Charn
    • Journal of Korean Society for Quality Management
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    • v.40 no.3
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    • pp.415-425
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    • 2012
  • Purpose: ISO 26000 is a newly emerging international standard for corporate social responsibility. This paper aims to derive core subjects of primary concern when introducing and practicing corporate social responsibility. Methods: Perceived performance and importance levels on core subjects in ISO 26000 are investigated, and a survey is conducted from members of organizations having published CSR reports. Frequency analysis, analysis of variance, cross tabulation and IP analysis are used to analyze surveyed data. Results: Items to be improved with high emphasis among 7 core subjects in ISO 26000 are organizational governance for public and private service sectors, fair operating practices for industrial goods manufacturing sectors, and organizational governance and environment for consumer goods manufacturing sectors. Human rights and labor practice are perceived as having high performances in comparison with importance. Conclusion: Organizations should find ways to build social responsibility into their governance systems and procedures with high priority.

Implementation of NON-ROS remote control software of TurtleBot 2 based Windows 10 IoT core (Windows 10 IoT Core 기반 Non-ROS TurtleBot2용 원격 제어 소프트웨어 구현)

  • Onesphore, Ingabire;Kim, Minyoung;Jang, Jongwook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2019.05a
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    • pp.111-114
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    • 2019
  • This paper intends to implement a software that controls TurtleBot 2 remotely. The moving of the robot TurtleBot 2 can be controlled using command control based on Windows 10 IoT core instead of the Robot Operating System (ROS). The implemented software allows the user to move remotely TurtleBot 2 in any specified direction and perform the monitoring such as reading feedback data from the robot. Through TCP/IP and serial communication technology, TurtleBot 2 can successfully receive command control and send feedback to the user. Using C# programming language, two Universal Windows Platform apps (client app and server app) have been implemented to allow communication between the user and TurtleBot 2. The result of this implementation has been verified and tested in an indoor platform.

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Efficient Backbone Core Tree Generation Algorithm (효과적인 Backbone Core Tree(BCT)생성 알고리즘)

  • 서현곤;김기형
    • Proceedings of the Korean Information Science Society Conference
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    • 2002.04a
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    • pp.214-216
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    • 2002
  • 본 논문에서는 many-to-many IP 멀티캐스팅을 위한 효율적인 Backbone Core Tree(BCT)생성 알고리즘에 대하여 제안한다. 본 논문의 제안기법은 Core Based Tree(CBT)에 기반을 두고 있다. CBT는 공유 트리를 이용하여 멀티캐스트 자료를 전달하기 때문에 Source Based Tree에 비하여 각 라우터가 유지해야 하는 상태 정보의 양에 적고 적용하기 간단하지만, Core 라우터 선택의 어려움과 트래픽이 Core로 집중되는 문제점을 가지고 있다. 이에 대한 보완책으로 Backbone Core Tree기법이 제안되었는데, 본 논문에서는 주어진 네트워크 위상 그래프에서 최소신장 트리를 만들고, 센트로이드를 이용하여 효율적인 BCT를 생성하는 알고리즘을 제안한다.

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FFT/IFFT IP Generator for OFDM Modems (OFDM 모뎀용 FFT/IFFT IP 자동 생성기)

  • Lee Jin-Woo;Shin Kyung-Wook;Kim Jong-Whan;Baek Young-Seok;Eo Ik-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.3A
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    • pp.368-376
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    • 2006
  • This paper describes a Fcore_GenSim(Parameterized FFT Core Generation & Simulation Program), which can be used as an essential If(Intellectual Property) in various OFDM modem designs. The Fcore_Gensim is composed of two parts, a parameterized core generator(PFFT_CoreGen) that generates Verilog-HDL models of FFT cores, and a fixed-point FFT simulator(FXP_FFTSim) which can be used to estimate the SQNR performance of the generated cores. The parameters that can be specified for core generation are FFT length in the range of 64 ~2048-point and word-lengths of input/output/internal/twiddle data in the range of 8-b "24-b with 2-b step. Total 43,659 FFT cores can be generated by Fcore_Gensim. In addition, CBFP(Convergent Block Floating Point) scaling can be optionally specified. To achieve an optimized hardware and SQNR performance of the generated core, a hybrid structure of R2SDF and R2SDC stages and a hybrid algorithm of radix-2, radix-2/4, radix-2/4/8 are adopted according to FFT length and CBFP scaling.